nanamake / vcd2jsonLinks
Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
☆40Updated last year
Alternatives and similar repositories for vcd2json
Users that are interested in vcd2json are comparing it to the libraries listed below
Sorting:
- Python library for operations with VCD and other digital wave files☆53Updated last month
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆49Updated last year
- Python interface for cross-calling with HDL☆45Updated this week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆71Updated 3 months ago
- HTML & Js based VCD viewer☆66Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆73Updated 3 weeks ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- Python Tool for UVM Testbench Generation☆55Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆81Updated 3 weeks ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆63Updated last month
- Generate address space documentation HTML from compiled SystemRDL input☆60Updated last month
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆73Updated this week
- hardware library for hwt (= ipcore repo)☆43Updated 2 weeks ago
- Running Python code in SystemVerilog☆71Updated 7 months ago
- Doxygen with verilog support☆40Updated 6 years ago
- Simple parser for extracting VHDL documentation☆73Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- Value Change Dump (VCD) parser☆38Updated last year
- Control and status register code generator toolchain☆164Updated last month
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- SystemVerilog frontend for Yosys☆186Updated this week
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- ideas and eda software for vlsi design☆51Updated this week
- A SystemVerilog source file pickler.☆60Updated last year
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆148Updated last week
- ☆111Updated last month
- WAL enables programmable waveform analysis.☆163Updated last month
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆21Updated 3 weeks ago