Alternatives and similar repositories for vcd2json

Users that are interested in vcd2json are comparing it to the libraries listed below

• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆51Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆66Updated this week
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆48Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated 2 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆58Updated last year
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• wavedrom / vcd
  Value Change Dump (VCD) parser
  ☆36Updated 5 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last month
• antmicro / verilator-verification-features-tests
  ☆22Updated this week
• stineje / sky130_cds
  This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Proce…
  ☆23Updated last year
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆58Updated 6 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆53Updated last month
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 10 months ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆40Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated 7 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated last week
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 4 months ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆44Updated 5 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆153Updated this week