pliu6 / vhd2vlLinks
vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
☆26Updated 9 years ago
Alternatives and similar repositories for vhd2vl
Users that are interested in vhd2vl are comparing it to the libraries listed below
Sorting:
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Wishbone controlled I2C controllers☆49Updated 7 months ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Verilog Repository for GIT☆33Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- USB Full Speed PHY☆44Updated 5 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆29Updated 6 years ago
- Another tiny RISC-V implementation☆56Updated 3 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Multi-Technology RAM with AHB3Lite interface☆23Updated last year
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 5 years ago
- JTAG Test Access Port (TAP)☆34Updated 10 years ago
- RISC-V compliant Timer IP☆12Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- Cortex-M0 DesignStart Wrapper☆19Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- ☆59Updated 3 years ago