Alternatives and similar repositories for cocotb-test

Users that are interested in cocotb-test are comparing it to the libraries listed below

• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆118Updated 3 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆257Updated 11 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆305Updated 3 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆73Updated last week
• raysalemi / Python4RTLVerification
  ☆174Updated 3 years ago
• svunit / svunit
  ☆208Updated 10 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆166Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated 2 months ago
• accellera-official / uvm-core
  ☆109Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆206Updated last year
• olofk / ipyxact
  Python-based IP-XACT parser and utilities
  ☆143Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated last month
• pyuvm / pyuvm
  The UVM written in Python
  ☆496Updated this week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 7 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆72Updated 3 months ago
• accellera / uvm
  ☆60Updated 9 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆112Updated 2 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆87Updated 4 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆269Updated this week
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆186Updated 4 months ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆75Updated 5 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆194Updated this week
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆108Updated last year
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆204Updated 8 years ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 11 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆176Updated 4 months ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆66Updated last year
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆39Updated 9 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆79Updated 6 years ago