wavedrom / vcd-samples
sample VCD files
☆36Updated last year
Alternatives and similar repositories for vcd-samples:
Users that are interested in vcd-samples are comparing it to the libraries listed below
- USB virtual model in C++ for Verilog☆29Updated 5 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆24Updated last month
- Wishbone interconnect utilities☆39Updated last month
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- GUI editor for hardware description designs☆28Updated last year
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆44Updated 2 years ago
- Portable HyperRAM controller☆54Updated 3 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆43Updated this week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 2 months ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- KiCad Library to make it easy to create both host boards and expansion boards and which are compatible with the Digilent "PMOD" specifica…☆38Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- USB Full Speed PHY☆42Updated 4 years ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆29Updated last month
- A padring generator for ASICs☆25Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- Virtual development board for HDL design☆41Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- Fabric generator and CAD tools graphical frontend☆12Updated 11 months ago
- ☆20Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- Library of reusable VHDL components☆28Updated last year