WaveDrom compatible python command line
☆118Jun 2, 2023Updated 3 years ago
Alternatives and similar repositories for wavedrompy
Users that are interested in wavedrompy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆40Aug 31, 2026Updated 2 months ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 4 years ago
- Unit testing for cocotb☆177Oct 17, 2026Updated 2 weeks ago
- Python package for writing Value Change Dump (VCD) files.☆136Oct 19, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python script to transform a VCD file to wavedrom format☆86Aug 18, 2022Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆149Oct 26, 2026Updated last week
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.☆12Jul 7, 2026Updated 3 months ago
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆43Jul 24, 2024Updated 2 years ago
- Python interface for cross-calling with HDL☆54Updated this week
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Aug 31, 2026Updated 2 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Staging area for new features of cocotb☆15Updated this week
- A command-line tool for displaying vcd waveforms.☆73Feb 19, 2024Updated 2 years ago
- The UVM written in Python☆572Updated this week
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- A Python to VHDL compiler☆18Apr 28, 2025Updated last year
- D3.js and ELK based schematic visualizer☆123May 13, 2026Updated 5 months ago
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- A sphinx extension that allows including wavedrom diagrams by using its text-based representation☆40Sep 3, 2024Updated 2 years ago
- An abstraction library for interfacing EDA tools☆803Sep 15, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- System on Chip toolkit for Amaranth HDL☆104May 23, 2026Updated 5 months ago
- Control and Status Register map generator for HDL projects☆149May 24, 2025Updated last year
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆80Updated this week
- cocotb: Python-based chip (RTL) verification☆2,558Updated this week
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Python library for operations with VCD and other digital wave files☆56May 19, 2026Updated 5 months ago
- Running Python code in SystemVerilog☆73May 8, 2026Updated 5 months ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- D3.js based wave (signal) visualizer☆68Jun 9, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Coverview☆36Oct 5, 2026Updated 3 weeks ago
- Generate verilog register file from systemRDL description☆14Feb 9, 2024Updated 2 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- Code generation tool for control and status registers☆476Sep 11, 2026Updated last month
- HDL symbol generator☆206Feb 2, 2023Updated 3 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆129Sep 22, 2026Updated last month
- Open-source EDA framework for RTL elaboration, netlist analysis, and transformation, with C++ and Python APIs☆166Updated this week