Alternatives and similar repositories for wavedrompy

Users that are interested in wavedrompy are comparing it to the libraries listed below

• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆120Updated 8 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆191Updated 2 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated 3 weeks ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆133Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 5 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆67Updated 2 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated 3 weeks ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆60Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆118Updated last month
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆63Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆40Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 5 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated last month
• wavedrom / vcd
  Value Change Dump (VCD) parser
  ☆36Updated 6 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆72Updated 10 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆64Updated last week
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated last week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 3 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 6 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆51Updated last month
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆60Updated 4 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 4 months ago