Alternatives and similar repositories for rars:

Users that are interested in rars are comparing it to the libraries listed below

• riscv-non-isa / riscv-asm-manual
  RISC-V Assembly Programmer's Manual
  ☆1,465Updated 3 weeks ago
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,538Updated this week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆605Updated 3 months ago
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆425Updated 7 months ago
• jameslzhu / riscv-card
  An unofficial assembly reference for RISC-V.
  ☆471Updated 2 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,338Updated last month
• riscv-software-src / riscv-tests
  ☆925Updated 2 months ago
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆993Updated 10 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆711Updated last week
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆693Updated 2 years ago
• riscv-collab / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC
  ☆3,685Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,152Updated 2 years ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,027Updated 3 weeks ago
• riscv-non-isa / riscv-elf-psabi-doc
  A RISC-V ELF psABI Document
  ☆731Updated last week
• riscv-software-src / opensbi
  RISC-V Open Source Supervisor Binary Interface
  ☆1,094Updated 3 weeks ago
• riscv / riscv-isa-manual
  RISC-V Instruction Set Manual
  ☆3,810Updated this week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,174Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆556Updated 5 months ago
• mikeroyal / RISC-V-Guide
  RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-…
  ☆547Updated last year
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,546Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆647Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,468Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,442Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆795Updated last week
• riscv / sail-riscv
  Sail RISC-V model
  ☆491Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,341Updated this week
• mortbopet / Ripes
  A graphical processor simulator and assembly editor for the RISC-V ISA
  ☆2,662Updated last week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,672Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,786Updated 3 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,328Updated 3 years ago