Alternatives and similar repositories for WebRISC-V:

Users that are interested in WebRISC-V are comparing it to the libraries listed below

• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆205Updated this week
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆108Updated 6 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆263Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆241Updated 3 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆130Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆225Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆84Updated 5 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆167Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆228Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆172Updated last year
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆306Updated 2 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆204Updated 4 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆307Updated 8 months ago
• SpinalHDL / NaxRiscv
  ☆275Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆264Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆166Updated 6 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆140Updated 3 months ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆138Updated 7 months ago
• chipsalliance / VeeR-ISS
  ☆129Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆127Updated 3 weeks ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆137Updated 7 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆454Updated this week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆129Updated 2 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆125Updated 5 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated 2 months ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆181Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆177Updated 7 months ago