Alternatives and similar repositories for WebRISC-V:

Users that are interested in WebRISC-V are comparing it to the libraries listed below

• SpinalHDL / NaxRiscv
  ☆281Updated last month
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆114Updated 6 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆229Updated 5 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆253Updated 2 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 5 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆171Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆95Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆190Updated 9 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆150Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆208Updated last week
• chipsalliance / VeeR-ISS
  ☆131Updated last year
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆312Updated 4 months ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆172Updated last week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆212Updated 4 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆156Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆131Updated last week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆151Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 8 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆275Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆144Updated 5 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated this week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆175Updated 4 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆181Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH2
  ☆232Updated 2 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆225Updated 5 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆406Updated 3 months ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆143Updated 9 months ago