Alternatives and similar repositories for WebRISC-V:

Users that are interested in WebRISC-V are comparing it to the libraries listed below

• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆236Updated 2 months ago
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆180Updated 2 years ago
• SpinalHDL / NaxRiscv
  ☆270Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆302Updated 7 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆220Updated 2 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆168Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆257Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆175Updated 6 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆207Updated 9 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆163Updated 5 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆120Updated 3 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆155Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆215Updated 11 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 2 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆107Updated 6 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆450Updated 2 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆266Updated 4 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆203Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆166Updated last year
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆313Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆204Updated 4 years ago
• chipsalliance / VeeR-ISS
  ☆127Updated last year
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 3 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆138Updated 2 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆154Updated this week
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆264Updated 4 years ago
• riscv-steel / riscv-steel
  RISC-V 32-bit microcontroller developed in Verilog
  ☆165Updated 2 months ago