Alternatives and similar repositories for jupiter

Users that are interested in jupiter are comparing it to the libraries listed below

• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆712Updated 3 years ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆807Updated 2 weeks ago
• vmware-archive / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆447Updated 4 years ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆664Updated 3 weeks ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,114Updated last week
• jameslzhu / riscv-card
  An unofficial assembly reference for RISC-V.
  ☆510Updated 11 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆492Updated last week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,468Updated 2 months ago
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆511Updated last year
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆698Updated 3 weeks ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆720Updated last month
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆218Updated 3 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆734Updated last month
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 4 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆214Updated last year
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆240Updated last year
• riscv-non-isa / riscv-arch-test
  ☆599Updated this week
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆473Updated 4 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆611Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆598Updated last year
• riscv-software-src / riscv-tests
  ☆1,068Updated this week
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆202Updated last year
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆241Updated 5 months ago
• riscvarchive / riscv-gcc
  ☆372Updated 2 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆159Updated 3 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆280Updated last week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆556Updated 2 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆872Updated 5 years ago