andrescv / jupiter
RISC-V Assembler and Runtime Simulator
☆428Updated 11 months ago
Alternatives and similar repositories for jupiter
Users that are interested in jupiter are comparing it to the libraries listed below
Sorting:
- RISC-V simulator for x86-64☆704Updated 3 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆444Updated 3 years ago
- Working Draft of the RISC-V Debug Specification Standard☆487Updated 2 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆323Updated 3 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆366Updated last year
- RISC-V Proxy Kernel☆632Updated 2 weeks ago
- educational microarchitectures for risc-v isa☆712Updated 2 months ago
- RISC-V Opcodes☆757Updated last week
- Simple RISC-V 3-stage Pipeline in Chisel☆572Updated 9 months ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,075Updated 2 months ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆210Updated last year
- VeeR EH1 core☆875Updated last year
- RISC-V Formal Verification Framework☆601Updated 3 years ago
- An unofficial assembly reference for RISC-V.☆488Updated 6 months ago
- A small, light weight, RISC CPU soft core☆1,398Updated 3 months ago
- Digital Design with Chisel☆832Updated this week
- ☆560Updated this week
- ☆997Updated 2 weeks ago
- ☆370Updated last year
- A directory of Western Digital’s RISC-V SweRV Cores☆865Updated 5 years ago
- Flexible Intermediate Representation for RTL☆740Updated 8 months ago
- VRoom! RISC-V CPU☆499Updated 8 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆652Updated 5 months ago
- RISC-V CPU Core☆324Updated 11 months ago
- RISC-V instruction set simulator built for education☆201Updated 3 years ago
- The root repo for lowRISC project and FPGA demos.☆598Updated last year
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆267Updated this week
- RISC-V Cores, SoC platforms and SoCs☆875Updated 4 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆236Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,065Updated 3 months ago