Alternatives and similar repositories for jupiter:

Users that are interested in jupiter are comparing it to the libraries listed below

• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆700Updated 3 years ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,056Updated 3 weeks ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆614Updated last month
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆563Updated 7 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆710Updated 2 weeks ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆478Updated last month
• riscv-software-src / riscv-tests
  ☆957Updated 3 weeks ago
• jameslzhu / riscv-card
  An unofficial assembly reference for RISC-V.
  ☆478Updated 4 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆734Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,371Updated last month
• riscv-non-isa / riscv-arch-test
  ☆549Updated last week
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆499Updated 6 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆818Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆673Updated 2 weeks ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,247Updated this week
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆366Updated last year
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆620Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆864Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,414Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated 3 weeks ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆209Updated last year
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆714Updated 3 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,848Updated last week
• riscvarchive / riscv-gcc
  ☆369Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆739Updated 7 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,029Updated last month
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆322Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago