Alternatives and similar repositories for venus

Users that are interested in venus are comparing it to the libraries listed below

• ThaumicMekanism / venus
  RISC-V instruction set simulator built for education
  ☆158Updated 2 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆150Updated 2 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆203Updated 5 years ago
• jameslzhu / riscv-card
  An unofficial assembly reference for RISC-V.
  ☆501Updated 9 months ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆192Updated last year
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆223Updated 4 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆215Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆156Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆589Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆792Updated 3 weeks ago
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆273Updated last year
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆477Updated last year
• riscv / sail-riscv
  Sail RISC-V model
  ☆597Updated this week
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆657Updated 3 weeks ago
• riscvarchive / risc-v-getting-started-guide
  The official RISC-V getting started guide
  ☆202Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• riscvarchive / riscv-gcc
  ☆372Updated 2 years ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆102Updated 6 years ago
• schoeberl / cae-lab
  Lab Material for CAE
  ☆41Updated 11 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆145Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 3 months ago
• riscv-software-src / homebrew-riscv
  homebrew (macOS) packages for RISC-V toolchain
  ☆351Updated 2 weeks ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆88Updated 3 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆257Updated 3 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆160Updated 5 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆150Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆153Updated 3 weeks ago
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆431Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated last year