Alternatives and similar repositories for venus:

Users that are interested in venus are comparing it to the libraries listed below

• ThaumicMekanism / venus
  RISC-V instruction set simulator built for education
  ☆155Updated 2 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆146Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆183Updated 8 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆209Updated 11 months ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆201Updated 4 years ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆169Updated 7 months ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆611Updated last month
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆149Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆563Updated 7 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆150Updated 2 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆172Updated last week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆320Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆222Updated 3 months ago
• riscv-non-isa / riscv-arch-test
  ☆543Updated this week
• andrescv / jupiter
  RISC-V Assembler and Runtime Simulator
  ☆426Updated 9 months ago
• jameslzhu / riscv-card
  An unofficial assembly reference for RISC-V.
  ☆476Updated 4 months ago
• riscv / sail-riscv
  Sail RISC-V model
  ☆506Updated this week
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆428Updated 11 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆594Updated 2 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆246Updated 2 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆246Updated last week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆704Updated this week
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆261Updated 7 years ago
• embench / embench-iot
  The main Embench repository
  ☆270Updated 6 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• riscv-software-src / riscv-tests
  ☆947Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆811Updated this week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆142Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆151Updated last year