Alternatives and similar repositories for documents

Users that are interested in documents are comparing it to the libraries listed below

• openrisc / or1200
  OpenRISC 1200 implementation
  ☆172Updated 9 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 4 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆274Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• riscv / riscv-test-env
  ☆50Updated 4 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 6 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 4 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆90Updated 7 years ago
• rgwan / kamikaze
  Light-weight RISC-V RV32IMC microcontroller core.
  ☆105Updated 8 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆112Updated 4 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 8 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆553Updated 2 weeks ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 5 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆296Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆372Updated 2 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆270Updated 4 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆154Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆361Updated 8 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆102Updated 6 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆193Updated last month
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆155Updated 7 years ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆140Updated last year
• riscvarchive / riscv-wiki
  ☆250Updated 8 years ago