Alternatives and similar repositories for SystemVerilog

Users that are interested in SystemVerilog are comparing it to the libraries listed below

• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 7 months ago
• accellera / uvm
  ☆57Updated 9 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆162Updated 2 weeks ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• accellera-official / uvm-core
  ☆97Updated last year
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆67Updated this week
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆142Updated 7 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last week
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆85Updated 4 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 11 months ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆93Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆147Updated last week
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆71Updated 5 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆107Updated 2 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆261Updated last week
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆288Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated this week
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated last week
• subbdue / systemverilog.io
  Code used in
  ☆197Updated 8 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆44Updated 3 years ago
• svunit / svunit
  ☆206Updated 7 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆191Updated 3 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆79Updated 3 years ago
• hjking / uvm_gen
  UVM Generator
  ☆47Updated last year