CEatBTU / FGPU
FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
☆54Updated 4 months ago
Alternatives and similar repositories for FGPU:
Users that are interested in FGPU are comparing it to the libraries listed below
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 6 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- ☆59Updated this week
- The multi-core cluster of a PULP system.☆90Updated this week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆95Updated 3 weeks ago
- ☆59Updated 3 years ago
- BlackParrot on Zynq☆39Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- RISC-V Nox core☆62Updated last month
- M-extension for RISC-V cores.☆30Updated 5 months ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- Open source ISS and logic RISC-V 32 bit project☆51Updated last week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated last week
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated 2 weeks ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆89Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆80Updated last week