CEatBTU / FGPULinks
FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
☆61Updated 8 months ago
Alternatives and similar repositories for FGPU
Users that are interested in FGPU are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆43Updated 2 years ago
- The multi-core cluster of a PULP system.☆108Updated this week
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 7 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 6 months ago
- ☆73Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆110Updated last month
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- RISC-V Nox core☆68Updated last month
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- Simple runtime for Pulp platforms☆49Updated last week
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆177Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆60Updated 4 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated 2 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year