xupsh / 2021_CN_WinterCampLinks
2021 Xilinx China Winter Camp
☆11Updated 4 years ago
Alternatives and similar repositories for 2021_CN_WinterCamp
Users that are interested in 2021_CN_WinterCamp are comparing it to the libraries listed below
Sorting:
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Huffman encoding core (Vivado HLS Project)☆12Updated 5 years ago
- OpenDLA for trying the demo and FPGA solution☆16Updated 2 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- Network on Chip for MPSoC☆26Updated last month
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆53Updated 6 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Updated 5 years ago
- ☆14Updated 9 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆23Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- ☆44Updated 5 years ago
- ☆33Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆16Updated 8 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 12 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- ☆13Updated 2 years ago