UCLA-VAST / CLINKLinks
Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
☆17Updated 6 years ago
Alternatives and similar repositories for CLINK
Users that are interested in CLINK are comparing it to the libraries listed below
Sorting:
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33Updated 6 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆74Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆45Updated 5 years ago
- ☆71Updated 5 years ago
- ☆64Updated 5 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- ☆72Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆75Updated 2 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- Vitis HLS Library for FINN☆213Updated this week
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- view at https://xupsh.github.io/ccc2021/☆23Updated 3 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆68Updated 6 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆154Updated 7 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- The second place winner for DAC-SDC 2020☆99Updated 3 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Updated 5 years ago