UCLA-VAST / CLINK
Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
☆17Updated 5 years ago
Alternatives and similar repositories for CLINK:
Users that are interested in CLINK are comparing it to the libraries listed below
- HLS implemented systolic array structure☆41Updated 7 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆46Updated 3 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆33Updated 2 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆54Updated 3 years ago
- ☆71Updated last year
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- ☆69Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆89Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆47Updated 6 years ago
- ☆33Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆42Updated 4 years ago
- An LSTM template and a few examples using Vivado HLS☆43Updated 8 months ago
- view at https://xupsh.github.io/ccc2021/☆24Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆49Updated 3 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆60Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆66Updated last year
- Benchmark framework of synaptic device technologies for a simple neural network☆28Updated 4 years ago
- RTL implementation of Flex-DPE.☆97Updated 4 years ago
- ☆56Updated 4 years ago
- MAESTRO binary release☆22Updated 5 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆132Updated last month
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆32Updated 5 years ago
- ☆88Updated 4 years ago
- The second place winner for DAC-SDC 2020☆96Updated 2 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆15Updated 3 years ago