dicearr / neuron-vhdl
Implementation of a neuron and 2 neuronal networks in vhdl
☆18Updated 7 years ago
Related projects: ⓘ
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆25Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆57Updated 7 years ago
- A multi-board Extended Kalman Filter (EKF)☆28Updated 5 years ago
- RISC-V ISA based 32-bit processor written in HLS☆15Updated 4 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆53Updated 6 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 6 years ago
- PYNQ Bootcamp 2019-2024 teaching materials.☆45Updated last month
- Generate testbench for your verilog module.☆35Updated 6 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆38Updated 2 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆14Updated 7 years ago
- Hand written number classification done in hardware (De1-SoC board) using neural networks☆24Updated 6 years ago
- Image Processing on FPGA using VHDL☆40Updated 10 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆13Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- PYNQ Composabe Overlays☆63Updated 3 months ago
- PYNQ, Neural network Language model, Overlay☆100Updated 5 years ago
- CNN accelerator☆26Updated 7 years ago
- Introductory examples for using PYNQ with Alveo☆47Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆17Updated 8 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆15Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆96Updated 4 years ago
- ☆23Updated this week
- Adding PR to the PYNQ Overlay☆17Updated 7 years ago
- ☆24Updated this week
- ☆34Updated 7 months ago
- All digital PLL☆24Updated 6 years ago
- ☆49Updated 5 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆26Updated 4 years ago