txstate-pcarch-blue / CPU
CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
☆21Updated 7 years ago
Alternatives and similar repositories for CPU:
Users that are interested in CPU are comparing it to the libraries listed below
- ☆26Updated 5 years ago
- Coarse Grained Reconfigurable Array☆19Updated 2 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- ☆12Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆33Updated 2 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆18Updated 11 years ago
- A repository for SystemC Learning examples☆67Updated 2 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆62Updated 8 years ago
- Modular Multi-ported SRAM-based Memory☆29Updated 5 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆39Updated 2 years ago
- SRAM☆22Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- DUTH RISC-V Microprocessor☆18Updated 4 months ago
- The OpenPiton Platform☆28Updated last year
- ☆26Updated 7 years ago
- ☆55Updated 4 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- ☆27Updated 4 years ago
- Project repo for the POSH on-chip network generator☆45Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- Contains commonly used UVM components (agents, environments and tests).☆29Updated 6 years ago