CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
☆21Apr 25, 2018Updated 7 years ago
Alternatives and similar repositories for CPU
Users that are interested in CPU are comparing it to the libraries listed below
Sorting:
- Implementation of different types of adder circuits☆16Jan 5, 2016Updated 10 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 9 years ago
- Implementing Different Adder Structures in Verilog☆74Sep 3, 2019Updated 6 years ago
- Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim☆13May 8, 2021Updated 4 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆16Mar 12, 2023Updated 3 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- Hardware Description Language on FPGA☆10Sep 18, 2023Updated 2 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Mar 9, 2026Updated last week
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- Coarse Grained Reconfigurable Array☆20Feb 18, 2026Updated last month
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- All the projects and assignments done as part of VLSI course.☆20Sep 23, 2020Updated 5 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- Netlist and Verilog Haskell Package☆19Nov 21, 2010Updated 15 years ago
- 108下 計算機組織 Computer Organization 李毅郎☆11Feb 22, 2021Updated 5 years ago
- ☆20Nov 16, 2014Updated 11 years ago
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- ☆14Feb 13, 2022Updated 4 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- ☆20Apr 2, 2023Updated 2 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆27May 12, 2020Updated 5 years ago
- Verilog implementation of a ultrasonic radar☆20Jan 7, 2018Updated 8 years ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 7 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 4 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)☆16Aug 16, 2021Updated 4 years ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- NYCU ICLAB 2025 spring codes & 心得☆21Jan 1, 2026Updated 2 months ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- ☆25Aug 9, 2022Updated 3 years ago
- Getting dense reconstruction based on kinfu_large_scale and orbslam2.☆14Jun 27, 2017Updated 8 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- Network on Chip for MPSoC☆28Feb 28, 2026Updated 3 weeks ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Sep 3, 2021Updated 4 years ago
- Self-hosted Todolist app written in Python☆10Apr 16, 2021Updated 4 years ago
- IC-contest 2012~2024☆23Apr 30, 2024Updated last year
- ☆22Jan 9, 2024Updated 2 years ago