CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
☆22Apr 25, 2018Updated 8 years ago
Alternatives and similar repositories for CPU
Users that are interested in CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Implementing Different Adder Structures in Verilog☆77Sep 3, 2019Updated 6 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 6 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Jun 19, 2026Updated last month
- Professor: C.H. Yang☆10Aug 16, 2025Updated 11 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- Coarse Grained Reconfigurable Array Generator☆20Jun 8, 2026Updated last month
- Hardware Description Language on FPGA☆11Sep 18, 2023Updated 2 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 5 months ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆17Jun 24, 2026Updated 3 weeks ago
- 108下 計算機組織 Computer Organization 李毅郎☆11Feb 22, 2021Updated 5 years ago
- FPU Generator☆20Updated this week
- Verilog implementation of a ultrasonic radar☆20Jan 7, 2018Updated 8 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated 10 months ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- ☆14Feb 13, 2022Updated 4 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- ☆22Apr 2, 2023Updated 3 years ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 8 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Oct 30, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)☆16Aug 16, 2021Updated 4 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆18Feb 23, 2022Updated 4 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- Getting dense reconstruction based on kinfu_large_scale and orbslam2.☆14Jun 27, 2017Updated 9 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- Network on Chip for MPSoC☆28Jun 16, 2026Updated last month
- ☆25Aug 9, 2022Updated 3 years ago
- IC-contest 2012~2024☆24Apr 30, 2024Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆44Sep 3, 2021Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆30Jan 26, 2024Updated 2 years ago
- ☆22Jan 9, 2024Updated 2 years ago
- Computer-Aided VLSI System Design☆25Oct 24, 2024Updated last year