Alternatives and similar repositories for fsm2sv

Users that are interested in fsm2sv are comparing it to the libraries listed below

• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 6 months ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 2 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆30Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated 3 weeks ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated last year
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆32Updated last week
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆38Updated 2 weeks ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆41Updated this week
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆31Updated 2 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆91Updated this week
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated last week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 5 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last week
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 4 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 4 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆75Updated 2 weeks ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 3 months ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆29Updated 8 months ago