liuwei9 / SpinalHDL_CNN_Accelerator
CNN accelerator implemented with Spinal HDL
☆17Updated 3 years ago
Alternatives and similar repositories for SpinalHDL_CNN_Accelerator:
Users that are interested in SpinalHDL_CNN_Accelerator are comparing it to the libraries listed below
- AXI总线连接器☆93Updated 4 years ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆25Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆13Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆72Updated 3 years ago
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- ☆14Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- IC Verification & SV Demo☆48Updated 3 years ago
- SpinalHDL AdderNet MNIST☆11Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆135Updated 5 years ago
- AXI Interconnect☆47Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆11Updated 4 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆30Updated 2 years ago
- AXI DMA 32 / 64 bits☆103Updated 10 years ago
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago
- ☆26Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆144Updated 11 months ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆98Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆24Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- upgrade to e203 (a risc-v core)☆38Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆32Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆56Updated 5 months ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago