Alternatives and similar repositories for sparc64soc

Users that are interested in sparc64soc are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆51Updated 7 months ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 6 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆77Updated 8 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• riscv / riscv-test-env
  ☆51Updated 3 months ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆90Updated 6 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆87Updated 4 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆106Updated 4 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆101Updated 8 months ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆78Updated 3 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 5 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆69Updated 7 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• sjohann81 / hf-risc
  HF-RISC SoC
  ☆39Updated last month
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆91Updated 5 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆176Updated 10 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆62Updated 4 years ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆76Updated 2 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆30Updated 4 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated 3 weeks ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆44Updated 7 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 9 months ago