freecores / sparc64socLinks
OpenSPARC-based SoC
☆69Updated 10 years ago
Alternatives and similar repositories for sparc64soc
Users that are interested in sparc64soc are comparing it to the libraries listed below
Sorting:
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- The OpenRISC 1000 architectural simulator☆76Updated 2 months ago
- ☆47Updated 2 months ago
- open-source SDKs for the SCR1 core☆73Updated 8 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- ☆63Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆88Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆74Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- 64-bit multicore Linux-capable RISC-V processor☆93Updated 2 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆48Updated 2 months ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- OmniXtend cache coherence protocol☆82Updated last month
- UNSUPPORTED INTERNAL toolchain builds☆43Updated this week
- Another tiny RISC-V implementation☆56Updated 3 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆77Updated 2 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago