freecores / sparc64socLinks
OpenSPARC-based SoC
☆68Updated 10 years ago
Alternatives and similar repositories for sparc64soc
Users that are interested in sparc64soc are comparing it to the libraries listed below
Sorting:
- The OpenRISC 1000 architectural simulator☆76Updated last month
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆85Updated 4 years ago
- ☆63Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆47Updated last month
- Demo SoC for SiliconCompiler.☆59Updated 3 weeks ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆59Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆64Updated 7 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- ☆21Updated 4 years ago
- 64-bit multicore Linux-capable RISC-V processor☆94Updated last month
- LatticeMico32 soft processor☆106Updated 10 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- ☆47Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- OpenRISC 1200 implementation☆171Updated 9 years ago
- RISC-V Nexus Trace TG documentation and reference code☆51Updated 5 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆99Updated 3 years ago