Alternatives and similar repositories for Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM

Users that are interested in Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM are comparing it to the libraries listed below

• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• mcjtag / tcam
  TCAM (Ternary Content-Addressable Memory) in Verilog
  ☆53Updated last year
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆49Updated 9 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆76Updated 6 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 11 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆44Updated 10 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆68Updated last year
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆37Updated 8 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆39Updated 5 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆77Updated 10 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 9 months ago
• oprecomp / DDR4_controller
  ☆62Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• merledu / OpenTCAM
  An open-source Ternary Content Addressable Memory (TCAM) compiler.
  ☆29Updated last year
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆57Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆59Updated 5 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated 2 months ago
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆20Updated 8 months ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆48Updated this week
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆46Updated last year
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆43Updated 2 years ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆86Updated 3 months ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆19Updated 7 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆66Updated 8 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆171Updated 3 months ago