AmeerAbdelhadi / Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
☆22Updated last week
Related projects ⓘ
Alternatives and complementary repositories for Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
- Verilog Content Addressable Memory Module☆102Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆41Updated 9 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆16Updated 5 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated last week
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆42Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- ☆16Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- ☆22Updated 8 months ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- ☆67Updated 10 years ago
- ☆47Updated 3 years ago
- Ethernet interface modules for Cocotb☆56Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆29Updated 3 years ago
- ☆25Updated 4 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆34Updated 8 years ago
- Simple hash table on Verilog (SystemVerilog)☆47Updated 8 years ago
- Systemverilog DPI-C call Python function☆19Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 3 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆15Updated 6 months ago
- Ethernet 10GE MAC☆44Updated 10 years ago
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago