Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
☆23Nov 10, 2024Updated last year
Alternatives and similar repositories for Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Users that are interested in Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆23Nov 10, 2024Updated last year
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Binary Content Addressable Memory (II-2D-BCAM)☆17Nov 10, 2024Updated last year
- This is an implemention of Lee-Moore's Shortest Path Maze Router with multi-sink nets support.☆13Feb 2, 2016Updated 10 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆58Oct 9, 2023Updated 2 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog Content Addressable Memory Module☆118Mar 2, 2022Updated 4 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Dec 16, 2019Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- Virtio implementation in SystemVerilog☆50Jan 23, 2018Updated 8 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- ☆23Sep 16, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆42Jun 9, 2022Updated 4 years ago
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆37Jul 19, 2024Updated 2 years ago
- Network packet parser generator☆53Sep 11, 2020Updated 5 years ago
- fpga based nes box☆23Sep 20, 2021Updated 4 years ago
- ☆13Apr 12, 2023Updated 3 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- Builds and parses PCIe Transport Layer Packets (TLPs)☆45Jul 21, 2022Updated 4 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Business Rule Engine Hardware Accelerator☆15Jun 18, 2020Updated 6 years ago
- Accelerating the regular expression matching on FPGA for applications in Networking and Bioinformatics.☆13Nov 24, 2017Updated 8 years ago
- ☆56Jun 22, 2022Updated 4 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Oct 8, 2019Updated 6 years ago
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Nov 24, 2014Updated 11 years ago
- Design of LDO using open source SKY130PDK☆17Aug 24, 2024Updated last year
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- 🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes…☆46Mar 27, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆16Feb 22, 2026Updated 5 months ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 4 years ago
- A c++ program to convert regular expression into Non-deterministic finite automata (NFA) using Thompson's construction.☆13Jul 28, 2018Updated 8 years ago
- ☆25May 8, 2015Updated 11 years ago
- FAST☆40Nov 11, 2016Updated 9 years ago