AmeerAbdelhadi / Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
☆23Updated 6 months ago
Alternatives and similar repositories for Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM:
Users that are interested in Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM are comparing it to the libraries listed below
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 6 months ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆48Updated last year
- SoC Based on ARM Cortex-M3☆30Updated this week
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Ethernet interface modules for Cocotb☆63Updated last year
- Systemverilog DPI-C call Python function☆22Updated 4 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆59Updated 4 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆74Updated 6 years ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆44Updated 10 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- ☆16Updated 3 years ago
- ideas and eda software for vlsi design☆50Updated last week
- ☆56Updated 4 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆29Updated this week
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆38Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- ☆27Updated 5 years ago