Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
☆23Nov 10, 2024Updated last year
Alternatives and similar repositories for Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Users that are interested in Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆23Nov 10, 2024Updated last year
- This is an implemention of Lee-Moore's Shortest Path Maze Router with multi-sink nets support.☆13Feb 2, 2016Updated 10 years ago
- Switched SRAM-based Multi-ported RAM☆19Nov 10, 2024Updated last year
- TCAM (Ternary Content-Addressable Memory) in Verilog☆59Oct 9, 2023Updated 2 years ago
- Modular Multi-ported SRAM-based Memory☆33Nov 8, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆16Dec 16, 2021Updated 4 years ago
- Verilog Content Addressable Memory Module☆118Mar 2, 2022Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- ☆23Sep 16, 2021Updated 5 years ago
- ☆42Jun 9, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- fpga based nes box☆23Sep 20, 2021Updated 4 years ago
- ☆13Apr 12, 2023Updated 3 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- Builds and parses PCIe Transport Layer Packets (TLPs)☆45Jul 21, 2022Updated 4 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 10 years ago
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated 2 years ago
- Business Rule Engine Hardware Accelerator☆15Jun 18, 2020Updated 6 years ago
- Accelerating the regular expression matching on FPGA for applications in Networking and Bioinformatics.☆13Nov 24, 2017Updated 8 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- 4096bit RSA project, with verilog code, python test code, etc☆47Oct 8, 2019Updated 6 years ago
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Nov 24, 2014Updated 11 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- 🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes…☆46Mar 27, 2026Updated 5 months ago
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆16Feb 22, 2026Updated 6 months ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 4 years ago
- A c++ program to convert regular expression into Non-deterministic finite automata (NFA) using Thompson's construction.☆13Jul 28, 2018Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- FAST☆40Nov 11, 2016Updated 9 years ago
- This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).☆13Apr 16, 2024Updated 2 years ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆30Sep 16, 2020Updated 6 years ago
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆17Oct 18, 2014Updated 11 years ago
- ☆35Jul 9, 2025Updated last year
- 上位机软件与下位机FPGA采集卡实现UDP通信,接收发送的正弦波信号帧,并保存到本地文件☆14Apr 27, 2022Updated 4 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago