xupsh / Digital-Design-Reference-DesignLinks
☆24Updated 9 years ago
Alternatives and similar repositories for Digital-Design-Reference-Design
Users that are interested in Digital-Design-Reference-Design are comparing it to the libraries listed below
Sorting:
- use Verilog HDL implemente bicubic interpolation in FPGA☆29Updated 6 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31Updated 6 years ago
- Verilog modules required to get the OV7670 camera working☆77Updated 7 years ago
- Demonstration of the AXI DMA engine on the ZedBoard☆55Updated 4 years ago
- ☆33Updated 6 years ago
- Video Stream Scaler☆40Updated 11 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- MIPI CSI-2 RX☆37Updated 4 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 8 months ago
- ☆34Updated 4 years ago
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆74Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 2 months ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆76Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆111Updated 5 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆63Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- configurable cordic core in verilog☆53Updated 11 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- USB 2.0 Device IP Core☆73Updated 8 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆60Updated 3 years ago
- ☆80Updated 3 years ago