xupsh / Digital-Design-Reference-Design
☆22Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for Digital-Design-Reference-Design
- MIPI CSI-2 RX☆29Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆63Updated this week
- mirror of https://git.elphel.com/Elphel/eddr3☆39Updated 7 years ago
- Verilog Code for a JPEG Decoder☆31Updated 6 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆32Updated 7 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31Updated 5 years ago
- Video Stream Scaler☆40Updated 10 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆20Updated 8 months ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- RTL for mipi serialize and deserialize☆11Updated 7 years ago
- Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor.☆20Updated 8 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- ☆28Updated 4 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆38Updated last year
- USB 2.0 Device IP Core☆52Updated 7 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆19Updated 8 years ago
- Project: Precise Measure of time delays in FPGA☆26Updated 7 years ago
- Demonstration of the AXI DMA engine on the ZedBoard☆51Updated 3 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆35Updated 5 years ago
- ☆18Updated 6 years ago
- ☆34Updated 9 years ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆62Updated 5 months ago
- 2019 SEU-Xilinx Summer School☆46Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆35Updated 7 years ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆12Updated 6 years ago
- configurable cordic core in verilog☆47Updated 10 years ago