This is just for Takk_Zynq_Labs test.
☆27Jan 14, 2022Updated 4 years ago
Alternatives and similar repositories for Takk_Zynq_Labs
Users that are interested in Takk_Zynq_Labs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different response…☆55Jun 28, 2018Updated 7 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- The project includes codes, specification, presentation and other information.☆27Feb 2, 2026Updated 3 months ago
- Attentionlego☆13Jan 24, 2024Updated 2 years ago
- Leaninig OpenCV 学习笔记,源码。☆11Nov 23, 2018Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 8 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 9 years ago
- Microshift Compression: An Efficient Image Compression Algorithm for Hardware☆36Apr 21, 2021Updated 5 years ago
- AWR1443 mmWave Demo 源码分析☆18Mar 3, 2018Updated 8 years ago
- ☆14Aug 23, 2023Updated 2 years ago
- Automatic Modulation Classification for 23 possible radar signal modulations.☆12Oct 17, 2023Updated 2 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…☆14May 6, 2020Updated 6 years ago
- 基于Zynq UltraScale+ MPSoC的AprilTag算法移植与加速☆13Nov 18, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Step by step tutorial for building CortexM0 SoC☆39Mar 29, 2022Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆70Jan 9, 2025Updated last year
- 关于数字IC的笔试面试题☆15Nov 17, 2019Updated 6 years ago
- This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…☆44Feb 17, 2019Updated 7 years ago
- Structured Binary Neural Networks for Image Recognition☆16Oct 12, 2022Updated 3 years ago
- The code for paper: Contrastive time–frequency learning for radar signal sorting☆18Sep 18, 2022Updated 3 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆63Dec 21, 2018Updated 7 years ago
- HDL & FPGA 学习和规范。CC-BY-NC-SA 4.0。☆16Jun 9, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 6 years ago
- Implemented The UART with FIFO☆15Jul 4, 2019Updated 6 years ago
- ☆19Dec 19, 2018Updated 7 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 5 years ago
- Simulating implement of LeNet network on Zynq-7020 FPGA☆28Mar 11, 2019Updated 7 years ago
- In this repository, w implement a direction of arrivals (DoA) classic and super-resolution algorithms such Multi-signals Classification (…☆25Sep 6, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆14Feb 17, 2023Updated 3 years ago
- Some of the fastest decoding range-based Asymetric Numeral Systems (rANS) codecs for x64☆20Sep 3, 2024Updated last year
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 2 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆15Jan 6, 2019Updated 7 years ago
- This repository is the open source code for our latest feasibility work: "Human Anomalous Gait Termination Recognition Via Through-the-Wa…☆26Jun 4, 2025Updated 11 months ago
- ☆15May 9, 2020Updated 5 years ago
- Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.☆24Sep 21, 2021Updated 4 years ago