JF-Tan / Takk_Zynq_LabsView external linksLinks
This is just for Takk_Zynq_Labs test.
☆27Jan 14, 2022Updated 4 years ago
Alternatives and similar repositories for Takk_Zynq_Labs
Users that are interested in Takk_Zynq_Labs are comparing it to the libraries listed below
Sorting:
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- Attentionlego☆12Jan 24, 2024Updated 2 years ago
- To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different response…☆54Jun 28, 2018Updated 7 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- ☆15May 9, 2020Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- AWR1443 mmWave Demo 源码分析☆18Mar 3, 2018Updated 7 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- The project includes codes, specification, presentation and other information.☆26Feb 2, 2026Updated 2 weeks ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆63Dec 21, 2018Updated 7 years ago
- ☆10Dec 18, 2016Updated 9 years ago
- Ethernet MAC 10/100 Mbps☆31Oct 31, 2021Updated 4 years ago
- Generator of verilog description for FPGA MobileNet implementation☆184Jun 23, 2022Updated 3 years ago
- AES加密解密算法的Verilog实现☆69Jan 17, 2016Updated 10 years ago
- A DNN Accelerator implemented with RTL.☆69Jan 9, 2025Updated last year
- PSAS Standard Operating Procedures and launch day instructions☆14Aug 5, 2020Updated 5 years ago
- Microshift Compression: An Efficient Image Compression Algorithm for Hardware☆34Apr 21, 2021Updated 4 years ago
- 爬取商品评论并对商品评论进行情感分类☆10Aug 14, 2017Updated 8 years ago
- This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog…☆36Mar 1, 2023Updated 2 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Jan 2, 2021Updated 5 years ago
- ☆153Dec 6, 2025Updated 2 months ago
- Step by step tutorial for building CortexM0 SoC☆39Mar 29, 2022Updated 3 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆21Jun 30, 2025Updated 7 months ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- Canonical normalizing flows☆10Apr 30, 2019Updated 6 years ago
- example files to follow the MOOC on RTL-SDR☆12Mar 18, 2017Updated 8 years ago
- LPC (Low Pin Count) interface peripheral module in pure Verilog☆17Jan 15, 2024Updated 2 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- iOS Cleanflight Configurator☆11Nov 11, 2017Updated 8 years ago
- 这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆96Sep 25, 2017Updated 8 years ago
- This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…☆44Feb 17, 2019Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Mar 17, 2022Updated 3 years ago
- ☆10Dec 7, 2021Updated 4 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆11Apr 2, 2025Updated 10 months ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- ☆12Jun 22, 2023Updated 2 years ago