JF-Tan / Takk_Zynq_LabsLinks
This is just for Takk_Zynq_Labs test.
☆26Updated 3 years ago
Alternatives and similar repositories for Takk_Zynq_Labs
Users that are interested in Takk_Zynq_Labs are comparing it to the libraries listed below
Sorting:
- ☆38Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 8 months ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆63Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- ☆66Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- ☆33Updated last year
- 中文:☆102Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆65Updated 6 years ago
- 3×3脉动阵列乘法器☆47Updated 6 years ago
- ☆10Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆37Updated 4 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 6 years ago
- ☆42Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- Zynq-7000 DPU TRD☆46Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- PYNQ学习资料☆166Updated 5 years ago
- ☆47Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆55Updated 3 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- 一个开源的FPGA神经网络加速器。☆177Updated 2 years ago
- 2019 SEU-Xilinx Summer School☆50Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆15Updated 6 years ago
- some interesting demos for starters☆84Updated 2 years ago