Alternatives and similar repositories for vcd

Users that are interested in vcd are comparing it to the libraries listed below

• pieter3d / simview
  ☆91Updated 3 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• ZipCPU / vgasim
  A Video display simulator
  ☆175Updated 8 months ago
• ldoolitt / vhd2vl
  ☆139Updated 3 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆253Updated last year
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆187Updated last year
• kevinpt / symbolator
  HDL symbol generator
  ☆200Updated 3 years ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆220Updated last month
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆67Updated 3 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆66Updated last year
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆65Updated 4 years ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆110Updated 5 months ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆130Updated last year
• wavedrom / vcdrom
  VCD viewer
  ☆101Updated 5 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆61Updated 3 weeks ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆189Updated 2 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆172Updated 2 months ago
• open-design / riscv-soc-cores
  ☆41Updated 4 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆72Updated 7 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆74Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆135Updated 7 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆129Updated 8 months ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆83Updated 5 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆115Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week