Alternatives and similar repositories for vcd

Users that are interested in vcd are comparing it to the libraries listed below

• pieter3d / simview
  ☆79Updated last year
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆174Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• ZipCPU / vgasim
  A Video display simulator
  ☆171Updated 2 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆120Updated 8 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆178Updated last month
• ldoolitt / vhd2vl
  ☆134Updated 7 months ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆121Updated 6 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 4 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 9 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆213Updated 3 weeks ago
• kevinpt / symbolator
  HDL symbol generator
  ☆191Updated 2 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆122Updated 4 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 9 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆111Updated last week
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 4 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆179Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆84Updated last month
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆99Updated 4 months ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆153Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆181Updated 6 months ago