Alternatives and similar repositories for vcd:

Users that are interested in vcd are comparing it to the libraries listed below

• pieter3d / simview
  ☆77Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆129Updated last month
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆173Updated 3 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆229Updated 5 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆113Updated last month
• kevinpt / symbolator
  HDL symbol generator
  ☆189Updated 2 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆94Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆109Updated 6 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last month
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆166Updated last year
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆208Updated 4 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆55Updated 4 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 8 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆58Updated 2 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆119Updated 2 weeks ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆228Updated 3 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆146Updated last week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆131Updated 2 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆111Updated last year
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆81Updated 8 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆128Updated last year
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆296Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆173Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆77Updated this week
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆73Updated 4 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆159Updated last week