Alternatives and similar repositories for vcd

Users that are interested in vcd are comparing it to the libraries listed below

• pieter3d / simview
  ☆87Updated 3 weeks ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆121Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 5 months ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆183Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆64Updated last year
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated last year
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• ZipCPU / vgasim
  A Video display simulator
  ☆174Updated 5 months ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆126Updated 11 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• ldoolitt / vhd2vl
  ☆137Updated 11 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆195Updated 2 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆82Updated 5 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆63Updated 4 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆168Updated this week
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆63Updated 3 weeks ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆93Updated last year
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 10 months ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆105Updated 2 months ago
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆136Updated 4 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 5 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆91Updated 3 weeks ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆68Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 3 weeks ago