kevinmehall / rust-vcdLinks
Read and write VCD (Value Change Dump) files in Rust
☆44Updated last year
Alternatives and similar repositories for rust-vcd
Users that are interested in rust-vcd are comparing it to the libraries listed below
Sorting:
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆80Updated last week
- Verilator Porcelain☆48Updated last year
- A simple digital waveform viewer with vi-like key bindings.☆138Updated 5 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆47Updated 7 months ago
- A hardware compiler based on LLHD and CIRCT☆263Updated last month
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- An HDL embedded in Rust.☆199Updated last year
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆56Updated this week
- End-to-end synthesis and P&R toolchain☆87Updated this week
- Logic circuit analysis and optimization☆43Updated last week
- The LLHD reference simulator.☆39Updated 4 years ago
- VHDL Language Support for VSCode☆67Updated 4 months ago
- Experimental flows using nextpnr for Xilinx devices☆244Updated 10 months ago
- Verilog parsing and generator crate.☆21Updated 5 years ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Hardware generator debugger☆75Updated last year
- System on Chip toolkit for Amaranth HDL☆92Updated 10 months ago
- Native Rust implementation of the FST waveform format from GTKWave.☆13Updated 2 weeks ago
- A dependency management tool for hardware projects.☆315Updated last month
- A command-line tool for displaying vcd waveforms.☆59Updated last year
- Low Level Hardware Description — A foundation for building hardware design tools.☆421Updated 3 years ago
- Integrated Circuit Layout☆54Updated 6 months ago
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Updated 5 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 11 months ago
- SystemVerilog linter☆355Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆117Updated last year
- PicoRV☆44Updated 5 years ago
- A SystemVerilog source file pickler.☆59Updated 10 months ago