avidan-efody / wave_rerunnerLinks
Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
☆63Updated 4 years ago
Alternatives and similar repositories for wave_rerunner
Users that are interested in wave_rerunner are comparing it to the libraries listed below
Sorting:
- ideas and eda software for vlsi design☆51Updated this week
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆138Updated last week
- Python interface for cross-calling with HDL☆47Updated 2 weeks ago
- Generate UVM register model from compiled SystemRDL input☆60Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated last week
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 months ago
- Running Python code in SystemVerilog☆71Updated 8 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆61Updated 3 weeks ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆74Updated last month
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆52Updated last week
- ☆114Updated 3 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆39Updated 9 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆74Updated 4 months ago
- SystemVerilog Linter based on pyslang☆31Updated 9 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Updated last year
- Test dashboard for verification features in Verilator☆29Updated this week
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- Making cocotb testbenches that bit easier☆36Updated 3 months ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆75Updated this week
- A SystemVerilog source file pickler.☆60Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Updated 2 weeks ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆119Updated 4 months ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago