avidan-efody / wave_rerunner
Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
☆59Updated 3 years ago
Alternatives and similar repositories for wave_rerunner:
Users that are interested in wave_rerunner are comparing it to the libraries listed below
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated this week
- This is the repository for the IEEE version of the book☆58Updated 4 years ago
- ideas and eda software for vlsi design☆50Updated 2 weeks ago
- Generate UVM register model from compiled SystemRDL input☆54Updated 8 months ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)☆74Updated 4 years ago
- ☆50Updated 8 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated 2 weeks ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- Running Python code in SystemVerilog☆68Updated 9 months ago
- ☆92Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆65Updated 6 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- Connecting SystemC with SystemVerilog☆40Updated 13 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆51Updated last week
- Announcements related to Verilator☆39Updated 4 years ago
- Introductory course into static timing analysis (STA).☆91Updated last week
- Code snippets from articles published on www.amiq.com/consulting/blog☆35Updated 10 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆57Updated 3 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆59Updated 4 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆59Updated 2 weeks ago
- UVM interactive debug library☆32Updated 7 years ago
- Doxygen with verilog support☆37Updated 6 years ago
- SystemVerilog VIP for AMBA APB protocol☆72Updated 3 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆113Updated last year