Alternatives and similar repositories for fst-tools

Users that are interested in fst-tools are comparing it to the libraries listed below

• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 8 months ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆83Updated last week
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 2 months ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆98Updated 3 years ago
• antmicro / verilator-verification-features-tests
  ☆27Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆51Updated 2 months ago
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated last week
• wavedrom / vcdrom
  VCD viewer
  ☆92Updated last week
• chipsalliance / espresso
  ☆40Updated 3 months ago
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆15Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆75Updated last year
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆24Updated 2 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 10 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• n-kremeris / verilator_basics
  ☆66Updated 2 years ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆63Updated 2 weeks ago
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆40Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 11 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆63Updated last week
• TsaiAnson / verif
  ☆12Updated 4 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 2 months ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆61Updated last month
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆48Updated 10 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆62Updated 7 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated last month
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆122Updated 9 months ago