Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
☆53Aug 7, 2023Updated 2 years ago
Alternatives and similar repositories for usb-test-suite-build
Users that are interested in usb-test-suite-build are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 6 years ago
- A header only C++11 library for functional coverage☆35Oct 5, 2022Updated 3 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- A configurable USB 2.0 device core☆31Jun 12, 2020Updated 6 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- ☆10May 27, 2026Updated last month
- USB Full-Speed core written in migen/LiteX☆17Sep 2, 2019Updated 6 years ago
- SPI flash MITM and emulation (QSPI is a WIP)☆20Jan 27, 2022Updated 4 years ago
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year
- ice40 USB Analyzer☆57Aug 8, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 7 years ago
- Board and connector definition files for nMigen☆30Sep 22, 2020Updated 5 years ago
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 6 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Oct 24, 2023Updated 2 years ago
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- Blackwire SpinalHDL components implementing WireGuard primitives☆16Aug 16, 2023Updated 2 years ago
- Unit testing for cocotb☆174Apr 18, 2026Updated 3 months ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Small footprint and configurable SPI core☆47Jul 10, 2026Updated 2 weeks ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆127Oct 3, 2025Updated 9 months ago
- Open source hardware down to the chip level!☆30Sep 24, 2021Updated 4 years ago
- Python package for writing Value Change Dump (VCD) files.☆135Nov 10, 2024Updated last year
- iCE40UP5K in an Adafruit Feather form factor☆26Aug 11, 2022Updated 3 years ago
- Pmod™ Compatible USB ULPI PHY☆14Apr 30, 2022Updated 4 years ago
- SystemVerilog (IEEE 1800-2017) Simulator☆64Updated this week
- Python interface to PCIE☆40Apr 30, 2018Updated 8 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆40Jan 11, 2026Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Python library for generating USB Descriptor byte strings using `struct` only.☆16Aug 13, 2021Updated 4 years ago
- standalone python host-side module to talk to OpenVizsla devices, based on LibOV [archived]☆18Feb 1, 2024Updated 2 years ago
- Top level CedarEDA integration package☆26Oct 22, 2024Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆147Jul 5, 2026Updated 2 weeks ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 5 years ago
- Yet Another Debug Transport☆30Jul 4, 2026Updated 2 weeks ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Dec 6, 2021Updated 4 years ago