antmicro / usb-test-suite-buildLinks
Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
☆51Updated last year
Alternatives and similar repositories for usb-test-suite-build
Users that are interested in usb-test-suite-build are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆59Updated 3 weeks ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Small footprint and configurable SPI core☆42Updated this week
- USB 1.1 Device IP Core☆21Updated 7 years ago
- sample VCD files☆37Updated last year
- Wishbone interconnect utilities☆41Updated 4 months ago
- ☆33Updated 2 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Small footprint and configurable JESD204B core☆44Updated 3 weeks ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated this week
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆38Updated 3 years ago