zylin / Verilog_VCD
https://pypi.python.org/pypi/Verilog_VCD
☆22Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for Verilog_VCD
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- ☆34Updated 9 months ago
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- Wishbone interconnect utilities☆36Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- The multi-core cluster of a PULP system.☆56Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆41Updated 3 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆31Updated 2 weeks ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆38Updated 4 months ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆27Updated 3 weeks ago
- ☆37Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆62Updated this week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆47Updated last week
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆16Updated 5 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 5 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆54Updated last year
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆20Updated 6 years ago
- RISCV model for Verilator/FPGA targets☆45Updated 5 years ago
- Open source process design kit for 28nm open process☆43Updated 6 months ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆56Updated 3 months ago
- Original RISC-V 1.0 implementation. Not supported.☆40Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆61Updated 7 months ago
- Spen's Official OpenOCD Mirror☆47Updated 8 months ago
- Yet Another RISC-V Implementation☆84Updated last month