Alternatives and similar repositories for csv2vcd

Users that are interested in csv2vcd are comparing it to the libraries listed below

• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated 3 months ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆38Updated 4 years ago
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated last week
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆31Updated 3 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated last week
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆47Updated 5 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆56Updated 2 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆23Updated 4 months ago
• cyrozap / python-bsdl-parser
  A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files
  ☆26Updated 2 weeks ago
• davidthings / hdelk
  Web-based HDL diagramming tool
  ☆79Updated 2 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• lnls-dig / general-cores
  general-cores
  ☆21Updated 2 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 5 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 3 years ago
• olofk / observer
  ☆41Updated 5 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated this week
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆36Updated 9 months ago
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• Cognoscan / VerilogCogs
  Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
  ☆20Updated 10 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆81Updated 4 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated last year
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago