tongchen126 / fpga_pcie_ethernetLinks
☆16Updated 3 years ago
Alternatives and similar repositories for fpga_pcie_ethernet
Users that are interested in fpga_pcie_ethernet are comparing it to the libraries listed below
Sorting:
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Updated last year
- Use ECP5 JTAG port to interact with user design☆32Updated 4 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Simplified environment for litex☆14Updated 4 years ago
- Siglent SDS1x0xX-E FPGA bitstreams☆42Updated 8 months ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Updated 3 years ago
- Utilities for the ECP5 FPGA☆18Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated 2 months ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆19Updated last year
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆31Updated 3 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆25Updated last week
- ☆20Updated 3 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 3 years ago
- ☆44Updated 6 months ago
- ECP5 FPGA in an "S7 Mini" form factor☆83Updated 4 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Updated 5 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated this week
- EVEREST: e-Versatile Research Stick for peoples☆36Updated 2 years ago
- Test of a RP2040 PMOD attached to a LiteX SoC.☆26Updated 2 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 6 years ago
- CRUVI Standard Specifications☆19Updated last year
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Updated 3 years ago
- Collection of projects for various FPGA development boards☆46Updated last year
- My pergola FPGA projects☆30Updated 4 years ago
- USB virtual model in C++ for Verilog☆31Updated 11 months ago
- WCH CH569 SerDes Reverse Engineering☆26Updated 3 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Updated 4 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago