IA-C-Lab-Fudan / KWS-SoCLinks
This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
☆54Updated 5 years ago
Alternatives and similar repositories for KWS-SoC
Users that are interested in KWS-SoC are comparing it to the libraries listed below
Sorting:
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆15Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- ☆13Updated 6 years ago
- LMS sound filtering by Verilog☆43Updated 5 years ago
- FFT generator using Chisel☆63Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Voice Activity Detector based on MFCC features and DNN model☆29Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- ☆46Updated 5 years ago
- verilog CNN generator for FPGA☆34Updated 5 years ago
- ☆66Updated 3 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆121Updated 13 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- ☆72Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 8 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- Open IP in Hardware Description Language.☆29Updated 2 years ago
- AHB DMA 32 / 64 bits☆58Updated 11 years ago
- CNN accelerator implemented with Spinal HDL☆157Updated 2 years ago
- Implement a bitonic sorting network on FPGA☆48Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆68Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆179Updated 6 years ago
- FPGA☆159Updated last year
- A scalable Eyeriss model in SystemC.☆33Updated 3 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆34Updated 7 years ago