Alternatives and similar repositories for KWS-SoC

Users that are interested in KWS-SoC are comparing it to the libraries listed below

• yiwangchunyu / AI-RISC
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆15Updated 4 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆62Updated 4 years ago
• dldldlfma / eyeriss_v1
  ☆13Updated 6 years ago
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆43Updated 5 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆156Updated last year
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 8 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆57Updated 11 years ago
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆47Updated 4 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆67Updated 7 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆69Updated last year
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆121Updated 12 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆28Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆109Updated 7 years ago
• CY0807 / ZYNQ_PL_CONV_ACC
  一个基于AXI接口的PL端卷积加速器，可由PS端调用
  ☆13Updated 2 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• dldldlfma / super_small_toy_tpu
  ☆46Updated 4 years ago
• alireza-shirzad / Cordic_tanh
  Verilog and matlab implementation of tanh using Cordic algorithm
  ☆11Updated 5 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 6 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 5 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆18Updated 4 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆114Updated 5 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆50Updated 6 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago