IA-C-Lab-Fudan / KWS-SoC
This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
☆48Updated 4 years ago
Alternatives and similar repositories for KWS-SoC:
Users that are interested in KWS-SoC are comparing it to the libraries listed below
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆14Updated 3 years ago
- Voice Activity Detector based on MFCC features and DNN model☆17Updated last year
- FFT generator using Chisel☆58Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- ☆33Updated 4 years ago
- ☆12Updated 5 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆31Updated 6 years ago
- Cortex M0 based SoC☆71Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- ☆36Updated 9 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- upgrade to e203 (a risc-v core)☆41Updated 4 years ago
- ARM中通过APB总线连接的UART模块☆63Updated 5 years ago
- ☆65Updated 2 years ago
- LMS sound filtering by Verilog☆39Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- ☆9Updated 4 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆51Updated 8 months ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- AI Chip project☆25Updated 3 years ago
- ☆60Updated 9 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆97Updated 4 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆14Updated 4 years ago