Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
☆65Nov 5, 2021Updated 4 years ago
Alternatives and similar repositories for vga-clock
Users that are interested in vga-clock are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- Compact FPGA game console☆167Nov 14, 2023Updated 2 years ago
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 8 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆37Jul 2, 2023Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆26Nov 15, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Oct 24, 2023Updated 2 years ago
- Utilities for the ECP5 FPGA☆17Aug 5, 2021Updated 4 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- A SoC for DOOM☆20Apr 11, 2021Updated 5 years ago
- A 6800 CPU written in nMigen☆49Jun 16, 2021Updated 5 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆71Jan 30, 2026Updated 5 months ago
- Miscellaneous ULX3S examples (advanced)☆87Feb 7, 2026Updated 5 months ago
- All Digital Radio Platform written in nmigen targeting FPGAs (for now)☆81Jun 1, 2021Updated 5 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Open source hardware down to the chip level!☆30Sep 24, 2021Updated 4 years ago
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- The Critical Path - a rambly FPGA blog☆52Sep 4, 2020Updated 5 years ago
- Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM☆24Oct 13, 2022Updated 3 years ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 5 years ago
- A curated list of Open Source PMOD boards☆44Jan 3, 2020Updated 6 years ago
- Project Peppercorn GateMate Test Cases☆17Feb 25, 2026Updated 5 months ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- ☆12Dec 22, 2020Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- UNIXv7 ported to RISC-V, specifically the Longnan Nano SBC☆13Mar 30, 2023Updated 3 years ago
- SRAM☆24Sep 6, 2020Updated 5 years ago
- Smol 2-stage RISC-V processor in nMigen☆26May 6, 2021Updated 5 years ago
- Some simple demo routines for the TinyFPGA BX☆16Sep 5, 2018Updated 7 years ago
- Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs☆136Jul 17, 2021Updated 5 years ago
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 3 years ago
- Eagle image importer☆22Jul 15, 2020Updated 6 years ago
- Doom classic port to lightweight RISC‑V☆108Jul 25, 2022Updated 4 years ago
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)☆259Aug 21, 2023Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆20Dec 23, 2020Updated 5 years ago
- FLIX-V: FPGA, Linux and RISC-V☆42Nov 5, 2023Updated 2 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆36Sep 5, 2021Updated 4 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 4 years ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆784Jan 28, 2026Updated 5 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 4 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago