m-asiatici / MSHR-rich
A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory access patterns.
☆18Updated 4 years ago
Alternatives and similar repositories for MSHR-rich:
Users that are interested in MSHR-rich are comparing it to the libraries listed below
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 5 years ago
- ☆23Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆46Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- ☆13Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆20Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆61Updated last year
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆45Updated 2 months ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆19Updated 9 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆28Updated 4 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆23Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆16Updated 5 months ago
- ☆24Updated 5 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year