A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory access patterns.
☆21Dec 3, 2020Updated 5 years ago
Alternatives and similar repositories for MSHR-rich
Users that are interested in MSHR-rich are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆20Nov 14, 2022Updated 3 years ago
- ☆15Jun 14, 2022Updated 3 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆24Jun 30, 2024Updated last year
- ☆14Jan 24, 2023Updated 3 years ago
- Source code for the evaluated benchmarks and proposed cache management technique, GRASP, in [Faldu et al., HPCA'20].☆18Jan 23, 2020Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Feb 22, 2024Updated 2 years ago
- ☆24May 23, 2023Updated 2 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆29Sep 16, 2020Updated 5 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14May 2, 2026Updated last week
- ☆23Apr 24, 2026Updated 2 weeks ago
- Evaluation of Deep Learning Network for Embedded Systems☆14Jul 27, 2016Updated 9 years ago
- Fast TLB simulator for RISC-V systems☆16May 16, 2019Updated 6 years ago
- ☆33Oct 28, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Jun 15, 2025Updated 10 months ago
- ☆13Jan 28, 2026Updated 3 months ago
- Code for VOTS2023 Challenge tracker☆10Jul 6, 2023Updated 2 years ago
- ☆15Mar 19, 2022Updated 4 years ago
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆10Jan 18, 2022Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆39Jan 13, 2023Updated 3 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- ☆16Jan 5, 2022Updated 4 years ago
- A cycle accurate emulator for the 6502 microprocessor☆19Oct 1, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AES implementation on FPGA☆13Apr 17, 2016Updated 10 years ago
- ☆12Aug 1, 2022Updated 3 years ago
- Reconsidering the Performance of GAE in Link Prediction☆17Jan 12, 2026Updated 3 months ago
- ☆24Dec 1, 2020Updated 5 years ago
- Base repo of a workable zsim on newer version of Ubuntu, with PIN-2.14 binary (the original zSim no longer works)☆14Nov 20, 2022Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- A guide on how to emulate an NVMe SPDM responder device with QEMU and Linux. Additionally, instructions on setting up and testing the (in…☆11Sep 3, 2024Updated last year
- Luthier, a GPU binary instrumentation tool for AMD GPUs☆28Updated this week
- Linux applications to manage, test and develop devices supporting DMTF Security Protocol and Data Model (SPDM)☆18May 1, 2026Updated last week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Open-source Verifiable Data Structures Server implementation☆13Aug 12, 2025Updated 8 months ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆42Oct 23, 2016Updated 9 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- Poker Hand Detection Using Yolov8☆15Feb 26, 2023Updated 3 years ago
- 国科大软件安全原理作业☆25Oct 27, 2020Updated 5 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 8 months ago
- SystemVerilog implemention of the TAGE branch predictor☆14May 26, 2021Updated 4 years ago