MEEPproject / fpga_shellLinks
MEEP FPGA Shell project, currently supporting Alveos u280 and u55c
☆14Updated last year
Alternatives and similar repositories for fpga_shell
Users that are interested in fpga_shell are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆26Updated last year
- ☆27Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- DaCH: dataflow cache for high-level synthesis.☆18Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆53Updated 10 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- BlackParrot on Zynq☆44Updated 5 months ago
- ☆24Updated 4 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Updated 5 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆26Updated 3 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆34Updated 10 months ago
- Algorithmic C Machine Learning Library☆26Updated 7 months ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆21Updated 2 years ago
- ☆17Updated last week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- corundum work on vu13p☆19Updated last year
- ☆77Updated 10 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆21Updated 9 years ago
- cycle accurate Network-on-Chip Simulator☆29Updated 2 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆56Updated 2 weeks ago
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆21Updated 11 months ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago