MEEPproject / fpga_shell
MEEP FPGA Shell project, currently supporting Alveos u280 and u55c
☆11Updated last year
Alternatives and similar repositories for fpga_shell:
Users that are interested in fpga_shell are comparing it to the libraries listed below
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- ☆26Updated 5 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆22Updated 3 years ago
- ☆54Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆23Updated 4 years ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆14Updated 6 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆54Updated last month
- ☆20Updated 2 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- ☆14Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆27Updated last year
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆20Updated 9 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- BlackParrot on Zynq☆38Updated last month
- ☆35Updated 4 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆22Updated last year
- ☆25Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year