MEEPproject / fpga_shellLinks
MEEP FPGA Shell project, currently supporting Alveos u280 and u55c
☆14Updated last year
Alternatives and similar repositories for fpga_shell
Users that are interested in fpga_shell are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆24Updated 5 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆37Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- DaCH: dataflow cache for high-level synthesis.☆20Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆26Updated 3 years ago
- ☆82Updated 11 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆22Updated 2 years ago
- ☆15Updated 7 months ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- corundum work on vu13p☆22Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- ☆29Updated last year
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Updated 6 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Updated 10 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆29Updated 5 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆22Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Updated 2 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- Open-Channel Open-Way Flash Controller☆21Updated 4 years ago
- ☆29Updated 6 years ago
- ☆72Updated 2 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago