MEEPproject / fpga_shellLinks
MEEP FPGA Shell project, currently supporting Alveos u280 and u55c
☆14Updated last year
Alternatives and similar repositories for fpga_shell
Users that are interested in fpga_shell are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆28Updated 6 years ago
- ☆24Updated 4 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆22Updated 10 years ago
- DaCH: dataflow cache for high-level synthesis.☆19Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆70Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆66Updated 3 weeks ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆54Updated 8 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆20Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆22Updated 2 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆35Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- ☆23Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆66Updated 4 months ago
- ☆72Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- ☆15Updated 5 months ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated last year
- ☆28Updated last year
- A High-Level DRAM Timing, Power and Area Exploration Tool☆29Updated 5 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Updated 2 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago