vickyiii / Quick-Start-Guide-for-HLSLinks
This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techniques you need to understand to use the Vitis HLS tool.
☆23Updated 2 years ago
Alternatives and similar repositories for Quick-Start-Guide-for-HLS
Users that are interested in Quick-Start-Guide-for-HLS are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆132Updated 4 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆109Updated 2 months ago
- eyeriss-chisel3☆41Updated 3 years ago
- 关于移植模型至gemmini的文档☆30Updated 3 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆130Updated 7 months ago
- ☆118Updated 5 years ago
- ☆36Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- ☆77Updated 5 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆95Updated 8 months ago
- ☆68Updated 6 years ago
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆172Updated 5 years ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆84Updated 3 months ago
- AMD University Program HLS tutorial☆110Updated 11 months ago
- ☆54Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆91Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆23Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆51Updated last month
- ☆42Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago