vickyiii / Quick-Start-Guide-for-HLS
This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techniques you need to understand to use the Vitis HLS tool.
☆19Updated 2 years ago
Alternatives and similar repositories for Quick-Start-Guide-for-HLS:
Users that are interested in Quick-Start-Guide-for-HLS are comparing it to the libraries listed below
- verilog实现TPU中的脉动阵列计算卷积的module☆72Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆39Updated 4 months ago
- 关于移植模型至gemmini的文档☆17Updated 2 years ago
- ☆98Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆135Updated 5 years ago
- ☆12Updated 9 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆22Updated last month
- AMD University Program HLS tutorial☆71Updated 2 months ago
- eyeriss-chisel3☆40Updated 2 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆94Updated last year
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆33Updated 5 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- ☆26Updated 5 years ago
- note about IC knowledge☆9Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- IC implementation of Systolic Array for TPU☆172Updated 2 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆174Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆13Updated 3 years ago
- A co-design architecture on sparse attention☆48Updated 3 years ago
- ☆13Updated last year
- ☆60Updated 6 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆137Updated 9 months ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆12Updated 8 months ago
- An FPGA Accelerator for Transformer Inference☆75Updated 2 years ago
- ☆59Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆23Updated last year