This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techniques you need to understand to use the Vitis HLS tool.
☆25Nov 9, 2022Updated 3 years ago
Alternatives and similar repositories for Quick-Start-Guide-for-HLS
Users that are interested in Quick-Start-Guide-for-HLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆19Jan 17, 2025Updated last year
- APB Logic☆26May 16, 2026Updated 3 weeks ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆36Mar 12, 2026Updated 3 months ago
- Testbenches for HDL projects☆23Jun 4, 2026Updated last week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- CNN accelerator implemented with Spinal HDL☆160Jan 29, 2024Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆20Sep 2, 2023Updated 2 years ago
- ☆49Apr 8, 2023Updated 3 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- ☆16Dec 9, 2023Updated 2 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆32Mar 7, 2024Updated 2 years ago
- RISC-V-based many-core neuromorphic architecture☆18May 24, 2026Updated 2 weeks ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆118Jun 15, 2025Updated 11 months ago
- Convert original MNIST database from http://yann.lecun.com/exdb/mnist/ into CSV format☆13Jun 10, 2018Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware v…☆14Nov 19, 2023Updated 2 years ago
- PREEMPT_RT Linux for Real-time Edge Software☆13Apr 22, 2026Updated last month
- A floating-point matrix multiplication implemented in hardware☆32Jan 5, 2021Updated 5 years ago
- A reading list for homomorphic encryption☆17Dec 28, 2022Updated 3 years ago
- MicroMix: Efficient Mixed-Precision Quantization with Microscaling Formats for Large Language Models☆28Apr 2, 2026Updated 2 months ago
- Neural network from scratch in Python using Numpy☆12May 28, 2017Updated 9 years ago
- Scraping repository of the most relevant topics with regards to Spatio-Temporal Neural Networks available in the arXiv archive. The repos…☆19Updated this week
- 基于FPGA的数字调制系统 :实现m序列作为信源,并通过按键来选择移位相加的初始值和步进值以及实现2ASK、2FSK、2PSK☆26Jun 4, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆49Mar 31, 2026Updated 2 months ago
- A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR☆23Oct 22, 2019Updated 6 years ago
- CNN simd based accelerator using Vitis HLS☆11Jul 15, 2022Updated 3 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆42Jan 12, 2016Updated 10 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆51May 20, 2026Updated 3 weeks ago
- SYSU-ARCH is a LAB that focuses on the use and extending of simulators.☆10Dec 19, 2022Updated 3 years ago
- This is an HLS-based FPGA accelerator implementation for openpose application.☆14Apr 5, 2019Updated 7 years ago
- ☆40Oct 21, 2025Updated 7 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations☆42Dec 14, 2013Updated 12 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆134Aug 27, 2024Updated last year
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- Instance segmentation of center pivot irrigation system in Brazil using Landsat images and Convolutional Neural Network☆11May 27, 2024Updated 2 years ago
- 一个基于AXI接口的PL端卷积加速器,可由PS端调用☆12Apr 15, 2023Updated 3 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆15Mar 26, 2024Updated 2 years ago
- A tool to generate optimized hardware files for univariate functions.☆30Apr 5, 2024Updated 2 years ago