vickyiii / Quick-Start-Guide-for-HLSLinks
This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techniques you need to understand to use the Vitis HLS tool.
☆25Updated 2 years ago
Alternatives and similar repositories for Quick-Start-Guide-for-HLS
Users that are interested in Quick-Start-Guide-for-HLS are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆134Updated 5 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆97Updated 9 months ago
- eyeriss-chisel3☆41Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆114Updated 3 months ago
- ☆69Updated 6 years ago
- 关于移植模型至gemmini的文档☆30Updated 3 years ago
- ☆120Updated 5 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- AMD University Program HLS tutorial☆116Updated 11 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆173Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆132Updated 8 months ago
- A systolic array matrix multiplier☆26Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- ☆10Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆91Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆36Updated 3 years ago
- ☆44Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆60Updated 3 months ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆88Updated 4 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆67Updated last month
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- ☆56Updated 6 years ago
- 基于FP16的二维脉动阵列电路设计☆11Updated 2 years ago
- ☆42Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆154Updated 7 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆71Updated 7 months ago