PrincetonUniversity / mapleLinks
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
☆21Updated last year
Alternatives and similar repositories for maple
Users that are interested in maple are comparing it to the libraries listed below
Sorting:
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆47Updated 6 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆52Updated 11 months ago
- gem5 repository to study chiplet-based systems☆85Updated 6 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- ☆22Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆73Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated this week
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- ☆41Updated 9 months ago
- cycle accurate Network-on-Chip Simulator☆31Updated this week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- ☆12Updated 3 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆41Updated this week
- CGRA framework with vectorization support.☆42Updated last week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆31Updated this week
- ☆32Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆71Updated 5 months ago