PrincetonUniversity / mapleLinks
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
☆21Updated last year
Alternatives and similar repositories for maple
Users that are interested in maple are comparing it to the libraries listed below
Sorting:
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- ☆20Updated 2 years ago
- CGRA framework with vectorization support.☆35Updated this week
- ☆47Updated 9 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 4 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆44Updated 10 months ago
- Advanced Architecture Labs with CVA6☆69Updated last year
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 3 weeks ago
- ☆18Updated 3 weeks ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆75Updated 3 weeks ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆80Updated last week
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆22Updated 10 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆36Updated 7 months ago
- DASS HLS Compiler☆29Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year
- gem5 repository to study chiplet-based systems☆82Updated 6 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆22Updated last year