PrincetonUniversity / mapleLinks
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
☆21Updated last year
Alternatives and similar repositories for maple
Users that are interested in maple are comparing it to the libraries listed below
Sorting:
- ☆22Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆45Updated 6 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆61Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆45Updated 11 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated 2 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆24Updated 10 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆52Updated 11 months ago
- gem5 repository to study chiplet-based systems☆84Updated 6 years ago
- ☆88Updated 3 weeks ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆68Updated 4 months ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- ☆40Updated 8 months ago
- HLS for Networks-on-Chip☆38Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 2 weeks ago
- ☆82Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- ☆28Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago