PrincetonUniversity / maple
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
☆18Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for maple
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆44Updated 4 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆92Updated 7 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆30Updated 8 months ago
- CGRA framework with vectorization support.☆19Updated last week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆94Updated last year
- Project repo for the POSH on-chip network generator☆43Updated last year
- ☆36Updated 7 months ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆68Updated 2 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- ☆84Updated 9 months ago
- Unit tests generator for RVV 1.0☆59Updated 3 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆50Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated last month
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆79Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated last month
- Virtuoso is a new simulator that focuses on modelling various memory management and virtual memory aspects.☆25Updated 11 months ago
- ☆86Updated 8 months ago
- ☆12Updated this week
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆120Updated last year
- ☆15Updated last year