PrincetonUniversity / mapleLinks
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
☆21Updated last year
Alternatives and similar repositories for maple
Users that are interested in maple are comparing it to the libraries listed below
Sorting:
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated 2 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆33Updated 2 months ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆20Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆29Updated 2 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- ☆15Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆58Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- HLS for Networks-on-Chip☆34Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆22Updated 2 years ago
- ☆15Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated 4 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 5 months ago
- ☆15Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- A hardware synthesis framework with multi-level paradigm☆39Updated 4 months ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago