PrincetonUniversity / maple
MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).
☆18Updated 9 months ago
Related projects ⓘ
Alternatives and complementary repositories for maple
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆47Updated 4 months ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆30Updated 9 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆95Updated 7 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆60Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- ☆36Updated 7 months ago
- ☆17Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- ☆15Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated this week
- Unit tests generator for RVV 1.0☆63Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆48Updated 4 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆79Updated 7 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆68Updated 2 months ago
- Chisel RISC-V Vector 1.0 Implementation☆57Updated this week
- chipyard in mill :P☆76Updated last year
- ☆31Updated last month
- ☆75Updated 2 years ago