Hardware Description Language Translator
☆19Aug 7, 2026Updated 2 months ago
Alternatives and similar repositories for verilog2vhdl
Users that are interested in verilog2vhdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Description Language Translator☆17Aug 7, 2026Updated 2 months ago
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated 2 months ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Aug 9, 2026Updated 2 months ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Aug 9, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Sep 1, 2026Updated last month
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Aug 9, 2026Updated 2 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆56Updated this week
- Network on Chip for MPSoC☆30Aug 7, 2026Updated 2 months ago
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 3 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 4 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Standard and Curated cores, tested and working.☆12Dec 29, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆18Sep 10, 2026Updated last month
- Episode I - RISCV CPU implementation tutorial for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆21Apr 7, 2026Updated 6 months ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 4 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆44Mar 7, 2024Updated 2 years ago
- Wi-Fi LDPC codec Verilog IP core☆21Jun 30, 2026Updated 3 months ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- System on Chip verified with UVM/OSVVM/FV☆37Aug 7, 2026Updated 2 months ago
- Open Source Software development Kit for Graphics GPU for Xilinx Zu+ Platform.☆19Feb 28, 2025Updated last year
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Drop In USB CDC ACM core for iCE40 FPGA☆37Sep 5, 2021Updated 5 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆22Mar 7, 2024Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆39Aug 7, 2026Updated 2 months ago
- A JSON library implemented in VHDL.☆87Jul 13, 2026Updated 3 months ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆21Feb 27, 2024Updated 2 years ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 3 months ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆71Jul 29, 2026Updated 2 months ago
- VHDL related news.☆27Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Real Digital Vivado IP Library☆10Nov 13, 2022Updated 3 years ago
- 最小和算法实现☆10Jul 12, 2020Updated 6 years ago
- ☆25Apr 18, 2021Updated 5 years ago
- Video Effects on VGA☆15Jan 7, 2019Updated 7 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆66Nov 14, 2025Updated 11 months ago
- A vector graphics renderer for bgfx, based on ideas from NanoVG and ImDrawList (Dear ImGUI)☆11Sep 26, 2026Updated 3 weeks ago
- LiteX based White Rabbit PCIe NIC developped for Warsaw University of Technology.☆27Oct 8, 2026Updated last week