PacoReinaCampo / verilog2vhdlLinks
Hardware Description Language Translator
☆18Updated 4 months ago
Alternatives and similar repositories for verilog2vhdl
Users that are interested in verilog2vhdl are comparing it to the libraries listed below
Sorting:
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 7 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- VHDL dependency analyzer☆24Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Proce…☆27Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Open FPGA Modules☆24Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- ☆33Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- ☆43Updated 7 months ago
- VHDL related news.☆26Updated this week
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆66Updated last week
- Generator for VHDL regular expression matchers☆15Updated 4 years ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- ☆15Updated 3 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 8 months ago
- hardware library for hwt (= ipcore repo)☆43Updated 3 weeks ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆46Updated 3 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- TCL framework to package Vivado IP-Cores☆14Updated 3 years ago