PacoReinaCampo / verilog2vhdlView external linksLinks
Hardware Description Language Translator
☆18Jan 27, 2026Updated 3 weeks ago
Alternatives and similar repositories for verilog2vhdl
Users that are interested in verilog2vhdl are comparing it to the libraries listed below
Sorting:
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- Hardware Description Language Translator☆17Jan 27, 2026Updated 3 weeks ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Feb 9, 2026Updated last week
- Network on Chip for MPSoC☆28Jan 27, 2026Updated 3 weeks ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- GSI Timing Gateware and Tools☆14Updated this week
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 2 years ago
- Direct Access Memory for MPSoC☆13Jan 27, 2026Updated 3 weeks ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Feb 10, 2026Updated last week
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 7 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- C++ library for AXI DMA with direct and scatter-gather support☆13Feb 22, 2022Updated 3 years ago
- 利用ZYNQ7020实现SAR数据采集系统，其中包含硬件设计代码、上位机、测试程序。☆14Feb 27, 2025Updated 11 months ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆15Apr 11, 2025Updated 10 months ago
- A collection of Opal Kelly provided design resources☆17Nov 7, 2025Updated 3 months ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Feb 9, 2026Updated last week
- ☆12Jul 20, 2022Updated 3 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Dec 3, 2025Updated 2 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆40Feb 24, 2025Updated 11 months ago
- Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.☆30Sep 13, 2025Updated 5 months ago
- An open-source HDL register code generator fast enough to run in real time.☆82Feb 2, 2026Updated 2 weeks ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆20Feb 27, 2024Updated last year
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Feb 9, 2026Updated last week
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated last year
- general-cores☆21Jul 16, 2025Updated 7 months ago
- A JSON library implemented in VHDL.☆82Feb 8, 2026Updated last week
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆38Updated this week
- Open FPGA Modules☆24Oct 8, 2024Updated last year
- VHDL functional blocks with their simulations and test sequences☆20Jan 26, 2026Updated 3 weeks ago
- VHDL dependency analyzer☆24Mar 10, 2020Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Dec 14, 2023Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Feb 10, 2026Updated last week