Alternatives and similar repositories for verilog2vhdl

Users that are interested in verilog2vhdl are comparing it to the libraries listed below

• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 6 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆17Updated 3 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆32Updated 4 years ago
• paulscherrerinstitute / PsiIpPackage
  TCL framework to package Vivado IP-Cores
  ☆14Updated 3 years ago
• abs-tudelft / vhdre
  Generator for VHDL regular expression matchers
  ☆15Updated 4 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆30Updated 5 years ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 3 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆22Updated last year
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 11 months ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated last year
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆29Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆33Updated last week
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 3 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆51Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆47Updated 5 years ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• Minres / RDL-Editor
  A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
  ☆12Updated last year
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated this week