Alternatives and similar repositories for Scala-Chisel-Learning-Journey

Users that are interested in Scala-Chisel-Learning-Journey are comparing it to the libraries listed below

• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆48Updated last year
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 7 months ago
• merledu / vaquita
  ☆18Updated 2 weeks ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 3 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆209Updated 2 weeks ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆27Updated this week
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• merledu / Riscv-Single-Cycle-Cores
  This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…
  ☆10Updated 2 years ago
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆88Updated 3 weeks ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆51Updated 2 years ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆67Updated last month
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆238Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆190Updated 3 years ago
• ucb-bar / testchipip
  ☆86Updated 2 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆88Updated this week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 4 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆76Updated 7 years ago
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆49Updated 4 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆137Updated 3 years ago
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆60Updated 10 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆121Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆155Updated 9 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆257Updated 3 years ago