Alternatives and similar repositories for Scala-Chisel-Learning-Journey

Users that are interested in Scala-Chisel-Learning-Journey are comparing it to the libraries listed below

• merledu / vaquita
  ☆18Updated 2 months ago
• merledu / Riscv-Single-Cycle-Cores
  This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…
  ☆10Updated 2 years ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆31Updated 6 months ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆45Updated 2 years ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆19Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆55Updated 8 months ago
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated 2 months ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆44Updated 11 months ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆63Updated this week
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆33Updated 5 years ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆131Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• Artityagi123456789 / 100DaysofRTL
  ☆17Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆93Updated last year
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆71Updated 2 years ago
• The-OpenROAD-Project / asap7
  ☆166Updated 2 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆97Updated 3 weeks ago
• arhamhashmi01 / rv32i-pipeline-processor
  This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
  ☆14Updated 3 months ago
• pulp-platform / fpu
  ☆50Updated 6 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆62Updated last year
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆34Updated 2 years ago
• VardhanSuroshi / Memory-Design-And-Testing
  The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
  ☆28Updated last year
• ReaLLMASIC / nanoGPT
  The simplest, fastest repository for training/finetuning medium-sized GPTs.
  ☆31Updated last week
• HunterBitos / Implementation-of-AMBA-AXI3-protocol
  Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…
  ☆14Updated 7 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆35Updated 9 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated last month
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆10Updated 9 months ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆49Updated 7 years ago