merledu / Scala-Chisel-Learning-Journey
This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.
☆12Updated 2 years ago
Alternatives and similar repositories for Scala-Chisel-Learning-Journey
Users that are interested in Scala-Chisel-Learning-Journey are comparing it to the libraries listed below
Sorting:
- ☆18Updated last month
- This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…☆10Updated 2 years ago
- The simplest, fastest repository for training/finetuning medium-sized GPTs.☆29Updated this week
- M-extension for RISC-V cores.☆30Updated 5 months ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆19Updated 4 months ago
- Pure digital components of a UCIe controller☆62Updated this week
- A Scala library for Context-Dependent Environments☆47Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆196Updated last week
- Vector Acceleration IP core for RISC-V*☆178Updated this week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆88Updated last year
- Provides various testers for chisel users☆100Updated 2 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆54Updated 9 months ago
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆237Updated last year
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A prototype GUI for chisel-development☆52Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆203Updated this week
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆131Updated 2 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆37Updated 4 years ago
- This repository contains the design files of RISC-V Pipeline Core☆42Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆98Updated last year
- An overview of TL-Verilog resources and projects☆78Updated last month
- ☆33Updated 6 years ago
- Introductory course into static timing analysis (STA).☆94Updated 3 weeks ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- ☆49Updated 6 years ago