Alternatives and similar repositories for Scala-Chisel-Learning-Journey:

Users that are interested in Scala-Chisel-Learning-Journey are comparing it to the libraries listed below

• merledu / vaquita
  ☆16Updated last week
• merledu / Riscv-Single-Cycle-Cores
  This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…
  ☆10Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆191Updated 3 weeks ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆29Updated 4 months ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆18Updated 2 months ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆59Updated 2 weeks ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆116Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆140Updated last month
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆51Updated 5 months ago
• ReaLLMASIC / nanoGPT
  The simplest, fastest repository for training/finetuning medium-sized GPTs.
  ☆26Updated this week
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆37Updated 2 years ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆39Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆172Updated last week
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆97Updated 4 years ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated 11 months ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆70Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆68Updated last year
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆23Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆185Updated this week
• freecores / round_robin_arbiter
  round robin arbiter
  ☆71Updated 10 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆72Updated 7 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆117Updated 9 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆58Updated last year