Alternatives and similar repositories for Scala-Chisel-Learning-Journey

Users that are interested in Scala-Chisel-Learning-Journey are comparing it to the libraries listed below

• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆20Updated 6 months ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated last year
• merledu / vaquita
  ☆18Updated 3 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆204Updated 2 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆180Updated 2 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 2 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆64Updated last week
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆58Updated 9 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆88Updated last week
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆49Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆152Updated 8 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆26Updated this week
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆236Updated last year
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆132Updated 5 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆101Updated last month
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆134Updated 3 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated 10 months ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆125Updated last year
• ucb-bar / testchipip
  ☆84Updated last month
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆203Updated 2 weeks ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆74Updated 7 years ago
• merledu / Riscv-Single-Cycle-Cores
  This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…
  ☆10Updated 2 years ago
• pulp-platform / fpu_ss
  CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor
  ☆11Updated 8 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆121Updated 4 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆255Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆215Updated this week