A simple and fast RISC-V JIT emulator.
☆162Aug 21, 2024Updated 2 years ago
Alternatives and similar repositories for rvemu
Users that are interested in rvemu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Learn how to write a minimal working linker from scratch☆117Apr 24, 2024Updated 2 years ago
- 本课程基于Rui的chibicc，@sunshaoce和@ksco将其由原来的X86架构改写为RISC-V 64架构，同时加入了大量的 中文注释，并且配有316节对应于每一个commit的课程，帮助读者可以层层推进、逐步深入的学习编译器的构造。☆366Jun 3, 2023Updated 3 years ago
- Compact and Efficient RISC-V RV32I[MAFC] emulator☆598Updated this week
- A fork of chibicc ported to RISC-V assembly.☆46May 19, 2022Updated 4 years ago
- Simple risc-v emulator, able to run linux, written in C.☆152Jul 27, 2026Updated 3 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- Super fast RISC-V ISA emulator for XiangShan processor☆354Updated this week
- A tiny C header-only risc-v emulator.☆2,195Dec 21, 2025Updated 10 months ago
- A super tiny RISC-V emulator that is able to run xv6.☆78Aug 16, 2022Updated 4 years ago
- FrontEnd Reverse-engineering Toolkit - CPU frontend uarch research framework☆14Updated this week
- RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Apr 11, 2020Updated 6 years ago
- ☆98Apr 22, 2024Updated 2 years ago
- A basic working RISCV emulator written in C☆82Feb 4, 2024Updated 2 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- jyy os enhanced☆13Jul 10, 2025Updated last year
- RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).☆964May 29, 2024Updated 2 years ago
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated 3 months ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- Build a minimal multi-tasking OS kernel for RISC-V from scratch☆511May 24, 2023Updated 3 years ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 9 months ago
- Generate Linux Perf event tables for Apple Silicon☆20Dec 16, 2025Updated 10 months ago
- gem5 相关中文笔记☆16Dec 2, 2021Updated 4 years ago
- only display GPU☆10Mar 6, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- riscv32i-cpu☆18Nov 20, 2020Updated 5 years ago
- A minimalist RISC-V system emulator capable of running Linux kernel with efficient event-driven scheduling☆315Updated this week
- ☆22Nov 3, 2025Updated last year
- A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered b…☆15Feb 14, 2024Updated 2 years ago
- ☆85Oct 29, 2024Updated 2 years ago
- RISC-V simulator for x86-64☆727Feb 5, 2022Updated 4 years ago
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆683Aug 13, 2024Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆54Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Tweaks to Fabrice Bellard's TinyEMU☆155Oct 14, 2023Updated 3 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆25Mar 31, 2026Updated 7 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 9 months ago
- RISCV CPU implementation in SystemVerilog☆32Oct 30, 2026Updated last week
- An open platform for exploring scale-up network systems.☆23Mar 16, 2026Updated 7 months ago
- NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching☆1,132Aug 12, 2026Updated 2 months ago
- The RISC-V Virtual Machine☆1,321Updated this week