yuhanzhu612 / OSCPU
我的一生一芯项目
☆16Updated 3 years ago
Alternatives and similar repositories for OSCPU:
Users that are interested in OSCPU are comparing it to the libraries listed below
- MIT6.175 & MIT6.375 Study Notes☆33Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆47Updated 4 months ago
- ☆74Updated this week
- A Study of the SiFive Inclusive L2 Cache☆59Updated last year
- ☆57Updated 2 months ago
- data preprocessing scripts for gem5 output☆17Updated 2 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 9 months ago
- ☆79Updated 3 weeks ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆13Updated 2 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆41Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- ☆61Updated 7 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 4 years ago
- Xiangshan deterministic workloads generator☆17Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- CQU Dual Issue Machine☆35Updated 8 months ago
- Open-source high-performance RISC-V processor☆28Updated this week
- riscv32i-cpu☆19Updated 4 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆143Updated 4 months ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆17Updated 3 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆29Updated 11 months ago
- ☆22Updated last year
- gem5 FS模式实验手册☆33Updated 2 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆34Updated 3 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆26Updated 2 years ago
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆24Updated 4 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆19Updated 6 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆39Updated 6 years ago