Alternatives and similar repositories for OSCPU

Users that are interested in OSCPU are comparing it to the libraries listed below

• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆42Updated 2 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆65Updated last year
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 3 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• OpenXiangShan / GEM5
  ☆97Updated this week
• cry-daniel / Computer-Architecture-Learning
  ☆63Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆40Updated 7 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 5 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆142Updated last year
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆51Updated 4 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆31Updated 2 years ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆29Updated 5 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• adamgallas / MIT_Bluespec_RISCV_Tutorial
  ☆22Updated 2 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated 2 years ago
• BUAA-CI-LAB / BHLA.README
  ☆16Updated last year
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 2 years ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆174Updated 4 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• cassuto / yamp-32
  NSCSCC 2020 - Yet Another MIPS Processor
  ☆14Updated 4 years ago