Alternatives and similar repositories for RV32ISC:

Users that are interested in RV32ISC are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆79Updated last month
• ysyx-ta / ysyx-summer-readings
  ☆62Updated 7 months ago
• OSCPU / yosys-sta
  ☆58Updated 2 months ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆15Updated 5 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆26Updated 2 years ago
• leesum1 / ysyx
  一生一芯项目
  ☆11Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 9 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆61Updated last year
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆24Updated last year
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆87Updated 3 weeks ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆40Updated last week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆145Updated 5 months ago
• OSCPU / chisel-playground
  ☆63Updated last month
• OpenXiangShan / GEM5
  ☆74Updated this week
• RV-BOSC / OpenNoC
  ☆128Updated 3 weeks ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆95Updated 9 months ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 2 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆127Updated 2 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆23Updated 2 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆19Updated 6 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆17Updated 2 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆55Updated 3 years ago
• lizhirui / DreamCoreV2
  ☆22Updated last year
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year