github-3rr0r / RV32ISC
A RISC-V RV32I ISA Single Cycle CPU
☆20Updated last year
Related projects: ⓘ
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆24Updated 2 years ago
- ☆75Updated last week
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- ☆12Updated this week
- ☆46Updated last month
- 体系结构研讨 + ysyx高阶大纲 (WIP☆95Updated 2 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 3 months ago
- ☆40Updated 2 months ago
- ☆50Updated last year
- CPU Design Based on RISCV ISA☆70Updated 3 months ago
- ☆55Updated last month
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆10Updated 5 years ago
- ☆61Updated last year
- ☆12Updated this week
- Collect some IC textbooks for learning.☆96Updated 2 years ago
- ☆35Updated 2 years ago
- ☆19Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 6 months ago
- ☆10Updated last year
- Open IP in Hardware Description Language.☆12Updated last year
- 一生一芯项目☆11Updated 10 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆54Updated 2 years ago
- ☆18Updated 9 months ago
- ☆54Updated this week
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 5 months ago
- AXI协议规范中文翻译版☆124Updated 2 years ago
- Modern co-simulation framework for RISC-V CPUs☆111Updated this week
- An AXI4 crossbar implementation in SystemVerilog☆112Updated 3 months ago
- Pick your favorite language to verify your chip.☆26Updated this week
- A Study of the SiFive Inclusive L2 Cache☆35Updated 8 months ago