Alternatives and similar repositories for ProjectN-CPU

Users that are interested in ProjectN-CPU are comparing it to the libraries listed below

• Yawei-Ding / ysyx_riscv64_cpu
  ☆72Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆194Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆147Updated last year
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 6 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆18Updated last year
• OSCPU / yosys-sta
  ☆90Updated 2 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆62Updated last year
• OSCPU / ysyx-workbench
  ☆161Updated last month
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆106Updated last year
• OSCPU / ysyxSoC
  ☆92Updated 4 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆33Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 8 months ago
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 4 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆129Updated last year
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• FanQinFred / Cache
  重庆大学计算机学院2018级计算机体系结构cache设计
  ☆11Updated 5 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆47Updated 3 years ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆16Updated 6 years ago
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆35Updated last year
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆41Updated 5 years ago
• leesum1 / ysyx
  一生一芯项目
  ☆18Updated 2 years ago
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆54Updated 3 years ago
• yizishun / ysyx-framework
  A framework for ysyx flow
  ☆13Updated last year
• USTC-System-Courses / CECS-Lab
  ☆42Updated 2 years ago
• xiaoan109 / ysyx-workbench
  一生一芯CPU/目前做到cache/后续主要考虑ASIC DV
  ☆22Updated last year
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year