Kristoff-starling / ProjectN-CPU
Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU
☆14Updated 2 years ago
Related projects: ⓘ
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆120Updated 2 months ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆46Updated 6 months ago
- ☆108Updated 2 weeks ago
- ☆55Updated last month
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆34Updated 4 years ago
- ☆40Updated 2 months ago
- 2022年龙芯杯个人赛 单发射110M(含icache)☆44Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆95Updated 2 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 3 months ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆24Updated 2 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆20Updated last year
- 2022龙芯杯个人赛三等奖作品☆13Updated 11 months ago
- ☆50Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 6 months ago
- NJU南京大学ICS课程2021年的PA实验,非常棒的一个大项目,受益匪浅!一栈式打通虚拟机NEMU、操作系统NLiteOS和应用层☆39Updated 2 years ago
- ☆10Updated last year
- ☆75Updated last week
- NJU Virtual Board☆217Updated last month
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆10Updated 5 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆60Updated 4 years ago
- ☆12Updated this week
- 一个单发射五级静态流水CPU,采用龙芯32位精简版指令集,支持异常和中断处理,使用AXI总线接口,已集成TLB模块☆9Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆65Updated last year
- ☆26Updated 11 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 5 months ago
- 一生一芯项目☆11Updated 10 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆60Updated 2 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆21Updated 6 months ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆109Updated 3 years ago