Tutorials on HLS Design
☆51Jan 16, 2020Updated 6 years ago
Alternatives and similar repositories for hls_tutorials
Users that are interested in hls_tutorials are comparing it to the libraries listed below
Sorting:
- Algorithmic C Machine Learning Library☆26Jan 6, 2026Updated 2 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Jan 6, 2026Updated 2 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆295Oct 30, 2025Updated 4 months ago
- ☆18Jul 20, 2022Updated 3 years ago
- Algorithmic C Datatypes☆136Jan 6, 2026Updated 2 months ago
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated 3 months ago
- ☆11Jan 21, 2021Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆27Jun 18, 2020Updated 5 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆205Nov 14, 2021Updated 4 years ago
- VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.☆17Nov 12, 2024Updated last year
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Oct 6, 2019Updated 6 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- ☆49Dec 10, 2019Updated 6 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Oct 3, 2023Updated 2 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Jun 23, 2023Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 5 years ago
- Algorithmic C Math Library☆67Jan 6, 2026Updated 2 months ago
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆23Oct 29, 2025Updated 4 months ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- Source files for Getting to Know Vivado course☆19Sep 2, 2020Updated 5 years ago
- ☆18Jul 12, 2024Updated last year
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆18Dec 11, 2018Updated 7 years ago
- ☆117Jul 15, 2021Updated 4 years ago
- Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge☆10Mar 6, 2023Updated 3 years ago
- ☆17Feb 9, 2023Updated 3 years ago
- NEural Minimizer for pytOrch☆47Jul 25, 2024Updated last year
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Nov 15, 2022Updated 3 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Dec 24, 2023Updated 2 years ago
- ☆17Jun 2, 2020Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆23Mar 31, 2021Updated 4 years ago
- ☆15Jul 7, 2020Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆51Feb 26, 2025Updated last year
- Hardware design with Chisel☆35Feb 9, 2023Updated 3 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆16Aug 24, 2022Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Jul 8, 2020Updated 5 years ago
- ☆47Aug 23, 2023Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Apr 18, 2019Updated 6 years ago
- ☆53Apr 19, 2019Updated 6 years ago