hlslibs / hls_tutorialsLinks
Tutorials on HLS Design
☆51Updated 6 years ago
Alternatives and similar repositories for hls_tutorials
Users that are interested in hls_tutorials are comparing it to the libraries listed below
Sorting:
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- Algorithmic C Machine Learning Library☆26Updated last month
- HLS for Networks-on-Chip☆39Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 7 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Public release☆58Updated 6 years ago
- ☆74Updated 5 years ago
- ☆29Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- Learn systemC with examples☆130Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- ☆66Updated 3 years ago
- ☆73Updated 7 years ago
- A repository for SystemC Learning examples☆73Updated 3 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 3 weeks ago
- Next generation CGRA generator☆118Updated this week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- ☆82Updated 11 years ago
- An open-source UCIe implementation☆82Updated last week
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- BlackParrot on Zynq☆48Updated this week
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- ☆45Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- ☆40Updated 6 years ago