sopynq / huffman-encoding-core
Huffman encoding core (Vivado HLS Project)
☆12Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for huffman-encoding-core
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆16Updated 6 years ago
- Verilog Code for a JPEG Decoder☆31Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- AHB Bus lite v3.0☆13Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆40Updated 3 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆18Updated 4 years ago
- CORDIC VLSI-IP for deep learning activation functions☆13Updated 5 years ago
- SoC Based on ARM Cortex-M3☆25Updated 5 months ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆18Updated 9 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆47Updated 7 years ago
- Wi-Fi LDPC codec Verilog IP core☆15Updated 5 years ago
- Implementation of the PCIe physical layer☆29Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆35Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆30Updated last year
- A tool for those who want to use Vivado's batch mode more easily☆15Updated 4 years ago
- Generic AXI master stub☆19Updated 10 years ago
- ☆20Updated 5 years ago
- ☆16Updated 5 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆14Updated 4 years ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆40Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- Build an open source, extremely simple DMA.☆19Updated 5 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago