sopynq / huffman-encoding-core
Huffman encoding core (Vivado HLS Project)
☆12Updated 5 years ago
Alternatives and similar repositories for huffman-encoding-core:
Users that are interested in huffman-encoding-core are comparing it to the libraries listed below
- Verilog Code for a JPEG Decoder☆33Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 4 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆15Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Networking Overlay on PYNQ☆48Updated 6 years ago
- DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.☆39Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆9Updated 3 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- ☆27Updated 6 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- ☆64Updated 2 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆35Updated 8 years ago
- digital recognition base on FPGA☆12Updated 5 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 7 years ago
- AHB DMA 32 / 64 bits☆53Updated 10 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆39Updated 3 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Updated 5 years ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆21Updated 5 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Gaussian noise generator Verilog IP core☆30Updated last year
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- This project describes how the cv2PYNQ python library was built☆20Updated 6 years ago
- CORDIC VLSI-IP for deep learning activation functions☆14Updated 5 years ago