IP prototyping in FPGA hardware
☆18Aug 28, 2018Updated 7 years ago
Alternatives and similar repositories for protoip
Users that are interested in protoip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Python Interior Point Optimization Solver☆13Jan 29, 2014Updated 12 years ago
- PhD Publications and Thesis on LASSO Model Predictive Control☆20Jun 2, 2019Updated 7 years ago
- Cookiecutter template to get you quickly started with an ESP32-based webserver project.☆15Dec 12, 2020Updated 5 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 4 months ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- JESD204B core for Migen/MiSoC☆37May 5, 2021Updated 5 years ago
- FPGA and Digital ASIC Build System☆84Updated this week
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 7 years ago
- CI Docker Images☆19Jan 1, 2021Updated 5 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- Mehrotra's Predictor-Corrector Interior Point Method☆14Nov 29, 2015Updated 10 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 10 years ago
- Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors☆23Dec 17, 2015Updated 10 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary t…☆13Oct 8, 2020Updated 5 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- Top level for the November shuttle☆12Nov 20, 2021Updated 4 years ago
- Example project that uses the AXI DMA peripheral to connect a custom AXI-Stream peripheral to memory☆14Feb 28, 2014Updated 12 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 3 months ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Testbenches for HDL projects☆23Jul 10, 2026Updated last week
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- This repository contains LaTeX class and template files to produce a PhD Thesis following the thesis guidelines of the University of Sout…☆25Aug 10, 2017Updated 8 years ago
- The implementation of AD9371 on KC705☆20Jun 10, 2025Updated last year
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆12Jun 4, 2021Updated 5 years ago
- Zynq PR Management☆13Apr 20, 2016Updated 10 years ago
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 9 years ago
- released krtkl schematics☆59Jun 29, 2018Updated 8 years ago
- ☆11Nov 19, 2025Updated 8 months ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆17Jul 11, 2015Updated 11 years ago