Hosseinabady / SDSoC-BenchmarksLinks
☆16Updated 4 years ago
Alternatives and similar repositories for SDSoC-Benchmarks
Users that are interested in SDSoC-Benchmarks are comparing it to the libraries listed below
Sorting:
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆72Updated 2 years ago
- ☆71Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- ☆30Updated 6 years ago
- ☆47Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 3 years ago
- ☆35Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Updated 6 years ago
- ☆17Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- ☆23Updated 4 years ago
- ☆17Updated 3 years ago
- ☆60Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆90Updated last year
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- ☆37Updated 7 months ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- Algorithmic C Machine Learning Library☆26Updated 10 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆25Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- ☆22Updated 3 years ago