Hosseinabady / SDSoC-Benchmarks
☆16Updated 4 years ago
Alternatives and similar repositories for SDSoC-Benchmarks:
Users that are interested in SDSoC-Benchmarks are comparing it to the libraries listed below
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆41Updated last month
- ☆35Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆34Updated 4 years ago
- ☆29Updated 5 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆71Updated 2 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- ☆26Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆37Updated 6 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆23Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- ☆33Updated 6 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆28Updated 6 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 4 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆20Updated last year
- ☆23Updated 4 years ago
- ☆35Updated 3 weeks ago
- ☆25Updated 11 months ago
- ☆3Updated 3 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- ☆16Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago