Hosseinabady / SDSoC-BenchmarksLinks
☆16Updated 4 years ago
Alternatives and similar repositories for SDSoC-Benchmarks
Users that are interested in SDSoC-Benchmarks are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆58Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆49Updated 8 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- ☆29Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆23Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆33Updated 6 years ago
- ☆36Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆71Updated 2 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- ☆35Updated 3 months ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- ☆4Updated 4 years ago
- ☆27Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- ☆25Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆71Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- ☆16Updated 4 years ago