Alternatives and similar repositories for mase

Users that are interested in mase are comparing it to the libraries listed below

• kachris / survey_HA_LLM
  A survey on Hardware Accelerated LLMs
  ☆59Updated 7 months ago
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆156Updated last month
• cornell-zhang / allo
  Allo: A Programming Model for Composable Accelerator Design
  ☆271Updated this week
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆150Updated this week
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆62Updated 5 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆58Updated last month
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• HLSTransform / submission
  ☆99Updated last year
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆146Updated 6 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆57Updated 5 months ago
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆44Updated 3 weeks ago
• mit-emze / cimloop
  ☆65Updated last week
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆83Updated last year
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆222Updated 2 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆174Updated last week
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• MartaAndronic / NeuraLUT
  NeuraLUT-Assemble
  ☆38Updated last week
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆110Updated 5 years ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆53Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆58Updated last week
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 11 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• pulp-platform / Deeploy
  DNN Compiler for Heterogeneous SoCs
  ☆44Updated last week
• aliemo / transfomers-silicon-research
  Research and Materials on Hardware implementation of Transformer Model
  ☆278Updated 5 months ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆58Updated 3 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆68Updated 5 months ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆136Updated 2 months ago
• Accelergy-Project / timeloop-accelergy-exercises
  Exercises for exploring the Fibertree, Timeloop and Accelergy tools
  ☆102Updated 4 months ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆272Updated last year