DeepWok / mase
Machine-Learning Accelerator System Exploration Tools
☆160Updated last week
Alternatives and similar repositories for mase:
Users that are interested in mase are comparing it to the libraries listed below
- A survey on Hardware Accelerated LLMs☆51Updated 3 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆140Updated this week
- ☆89Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆51Updated last month
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆129Updated last year
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆30Updated last month
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆113Updated 2 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆145Updated last month
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- RTL implementation of Flex-DPE.☆99Updated 5 years ago
- Allo: A Programming Model for Composable Accelerator Design☆228Updated this week
- ☆56Updated this week
- Repository to host and maintain scale-sim-v2 code☆290Updated 2 weeks ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆218Updated 2 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆168Updated this week
- Research and Materials on Hardware implementation of Transformer Model☆258Updated 2 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆52Updated 3 months ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆119Updated 11 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆60Updated 3 months ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆51Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆136Updated 2 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆40Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated last week
- ☆50Updated last month
- Implementation of Microscaling data formats in SystemVerilog.☆18Updated 8 months ago