IEEE-NITK / VLSI_design-of-RISC
IEEE Executive project for the year 2021-2022
☆7Updated 2 years ago
Alternatives and similar repositories for VLSI_design-of-RISC:
Users that are interested in VLSI_design-of-RISC are comparing it to the libraries listed below
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 4 months ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- ☆11Updated last week
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- ☆16Updated last year
- Synchronous FIFO Testbench☆10Updated 2 years ago
- ☆16Updated 9 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆31Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆19Updated 10 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆13Updated 9 months ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆80Updated last year
- ☆13Updated 10 months ago
- AXI Interconnect☆47Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- ☆16Updated last year
- SystemVerilog UVM testbench example☆29Updated 8 months ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- ☆13Updated 11 months ago
- PCIE 5.0 Graduation project (Verification Team)☆57Updated 11 months ago
- ☆10Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆21Updated 3 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago