IEEE Executive project for the year 2021-2022
☆11Nov 22, 2022Updated 3 years ago
Alternatives and similar repositories for VLSI_design-of-RISC
Users that are interested in VLSI_design-of-RISC are comparing it to the libraries listed below
Sorting:
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆17Dec 16, 2017Updated 8 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- Quite OK image compression Verilog implementation☆23Nov 27, 2024Updated last year
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Sep 28, 2017Updated 8 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆14Mar 17, 2019Updated 7 years ago
- Quite OK Image FPGA Encoder and Decoder☆24May 20, 2023Updated 2 years ago
- This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU…☆30Dec 12, 2021Updated 4 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- An open source 3GPP LTE implementation. (GitHub import of https://sourceforge.net/projects/openlte/)☆10Mar 7, 2017Updated 9 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Jan 4, 2018Updated 8 years ago
- simulator for riscv instruction set☆25Sep 24, 2022Updated 3 years ago
- IEEE Research paper with Code. Top class collection of IEEE Projects. Machine learning, Cryptography, Data science and Blockchain Project…☆20Jan 6, 2023Updated 3 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Jul 14, 2019Updated 6 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- Advanced encryption standard implementation in verilog.☆31Oct 2, 2022Updated 3 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆13Jun 9, 2021Updated 4 years ago
- ☆18Oct 6, 2025Updated 5 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Dec 10, 2021Updated 4 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Mar 5, 2017Updated 9 years ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- BlackParrot on Zynq☆53Mar 16, 2026Updated last week
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated 11 months ago
- AES☆15Oct 4, 2022Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- A pipelined brainfuck softcore in Verilog☆19Aug 5, 2014Updated 11 years ago
- Zedboard projects☆11May 15, 2016Updated 9 years ago
- AES-128 Encryption☆10Jul 17, 2014Updated 11 years ago
- TorghostNG - Reroute your internet traffic anonymized through Tor. Rewritten from TorGhost with Python 3☆26Jul 14, 2024Updated last year
- Digital image processing helps replace several mundane activities. My project in final year was ‘Application Control using Hand Gesture R…☆18Mar 27, 2017Updated 8 years ago
- Submission template for Tiny Tapeout 10 - Verilog HDL Projects☆26Jun 27, 2025Updated 8 months ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆14Feb 20, 2026Updated last month
- ☆21Mar 5, 2023Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago