IEEE Executive project for the year 2021-2022
☆11Nov 22, 2022Updated 3 years ago
Alternatives and similar repositories for VLSI_design-of-RISC
Users that are interested in VLSI_design-of-RISC are comparing it to the libraries listed below
Sorting:
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆17Dec 16, 2017Updated 8 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- Advanced encryption standard implementation in verilog.☆31Oct 2, 2022Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Dec 10, 2021Updated 4 years ago
- FIR band-pass filter using Verilog HDL.☆12Sep 6, 2020Updated 5 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- An open source 3GPP LTE implementation. (GitHub import of https://sourceforge.net/projects/openlte/)☆10Mar 7, 2017Updated 8 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆10Dec 13, 2020Updated 5 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Sep 28, 2017Updated 8 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- BlackParrot on Zynq☆50Feb 11, 2026Updated 2 weeks ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12May 29, 2021Updated 4 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆11Sep 30, 2020Updated 5 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆10Feb 20, 2026Updated last week
- A series of simulations organized as homework assignments that were part of the course on Neuromorphic Engineering at IIT Bombay (course …☆10Jul 19, 2016Updated 9 years ago
- Example of a full DC synthesis script for a simple design☆13Feb 25, 2019Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Jan 4, 2018Updated 8 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- EC499: Major Project☆10Jun 25, 2023Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Jul 28, 2021Updated 4 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆13Nov 28, 2019Updated 6 years ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- ☆15Jun 7, 2022Updated 3 years ago
- Zedboard projects☆11May 15, 2016Updated 9 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- AES-128 Encryption☆10Jul 17, 2014Updated 11 years ago
- In this project, the simulation of simple digital hearing aid was developed using MATLAB programming language. The implementation of this…☆10Nov 11, 2021Updated 4 years ago
- A 2D convolution hardware implementation written in Verilog☆51Dec 21, 2020Updated 5 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆13Jun 9, 2021Updated 4 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆14Jan 6, 2019Updated 7 years ago
- ☆14May 13, 2022Updated 3 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 6 years ago
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Apr 21, 2022Updated 3 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated 11 months ago