Alternatives and similar repositories for VLSI_design-of-RISC

Users that are interested in VLSI_design-of-RISC are comparing it to the libraries listed below

• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆31Updated 5 years ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆22Updated 4 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated 3 months ago
• shubhi704 / APB-Protocol
  ☆46Updated 4 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆29Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆19Updated last month
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆15Updated 2 years ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆35Updated 9 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆50Updated 3 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 10 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆62Updated 2 years ago
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆18Updated last month
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆66Updated 4 years ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆32Updated last week
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆20Updated last year
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆19Updated 6 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆53Updated last year
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆15Updated 4 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆49Updated 5 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆78Updated last year
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 4 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆33Updated last year