IEEE-NITK / VLSI_design-of-RISC
IEEE Executive project for the year 2021-2022
☆9Updated 2 years ago
Alternatives and similar repositories for VLSI_design-of-RISC:
Users that are interested in VLSI_design-of-RISC are comparing it to the libraries listed below
- System Verilog using Functional Verification☆10Updated 11 months ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆22Updated last year
- ☆19Updated 2 years ago
- ☆16Updated last year
- ☆17Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- ☆12Updated last month
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- Maven Silicon Project☆17Updated 6 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 7 months ago
- AXI Interconnect☆47Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- UVM Testbench for synchronus fifo☆16Updated 4 years ago
- ☆25Updated 3 years ago
- RTL Design and Verification☆11Updated 4 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- A complete UVM TB for verification of single port 64KB RAM