black-parrot-hdk / zynq-parrot

Related projects ⓘ

Alternatives and complementary repositories for zynq-parrot

• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆59Updated this week
• oprecomp / DDR4_controller
  ☆47Updated 3 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 7 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆47Updated 2 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆49Updated 10 months ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆48Updated 5 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆93Updated this week
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆67Updated 10 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 4 months ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆31Updated 3 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆26Updated 4 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆41Updated 3 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆45Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆137Updated 3 weeks ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆31Updated last year
• samehattia / StateMover
  StateMover is a checkpoint-based debugging framework for FPGAs.
  ☆17Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated 3 weeks ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆44Updated 5 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆22Updated last month
• chipsalliance / uvm-verilator
  ☆75Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆62Updated 4 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• Xilinx / pcie_qdma_ats_example
  ☆22Updated 3 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆56Updated 4 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆40Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆32Updated last year