BlackParrot on Zynq
☆56Jun 17, 2026Updated last month
Alternatives and similar repositories for zynq-parrot
Users that are interested in zynq-parrot are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Apr 15, 2025Updated last year
- Repository gathering basic modules for CDC purpose☆63Dec 31, 2019Updated 6 years ago
- A Linux-capable RISC-V multicore for and by the world☆824Jul 13, 2026Updated 3 weeks ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- ☆15Nov 30, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- AES☆16Oct 4, 2022Updated 3 years ago
- ☆42Jun 24, 2026Updated last month
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆15Jul 7, 2026Updated last month
- ☆35Jan 21, 2021Updated 5 years ago
- ☆36Jul 29, 2026Updated last week
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code（使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- Generic Register Interface (contains various adapters)☆141Updated this week
- ☆12Apr 7, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"☆17May 20, 2022Updated 4 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- VHDL functional blocks with their simulations and test sequences☆20Jul 3, 2026Updated last month
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- GEMM and GEMM-Ops accelerator for PULP systems☆113Updated this week
- Branch Predictor Optimization for BlackParrot☆15Mar 24, 2024Updated 2 years ago
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A 256-bit block cipher based on SPN design, supporting key sizes of 256/384/512 bits☆14Feb 26, 2023Updated 3 years ago
- ☆17Apr 25, 2024Updated 2 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆161Oct 31, 2024Updated last year
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- Handwritten GEMM using Intel AMX (Advanced Matrix Extension)☆17Jan 11, 2025Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆33Nov 3, 2025Updated 9 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 2 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated 9 months ago
- Userspace DMA library for Zynq-based SoCs☆16Jan 22, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆226Updated this week
- ☆28Aug 3, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆677Jul 7, 2026Updated last month
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆23Updated this week
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆62Jul 5, 2022Updated 4 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆31Dec 1, 2016Updated 9 years ago