A pipelined brainfuck softcore in Verilog
☆20Aug 5, 2014Updated 12 years ago
Alternatives and similar repositories for bfcpu2
Users that are interested in bfcpu2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- DirectDraw HAL implementation for VMDisp9x driver☆15May 9, 2026Updated 3 months ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Cross EDA Abstraction and Automation☆42Updated this week
- ☆18Jul 9, 2026Updated last month
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 9 years ago
- IEEE Executive project for the year 2021-2022☆12Nov 22, 2022Updated 3 years ago
- APB Logic☆29Aug 6, 2026Updated last week
- [WIP] ConfigX - Settings Management☆13Mar 6, 2024Updated 2 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12Feb 28, 2026Updated 5 months ago
- Open Source Software development Kit for Graphics GPU for Xilinx Zu+ Platform.☆19Feb 28, 2025Updated last year
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 14 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- n-dimensional kdtree spatial indexing☆17Apr 7, 2022Updated 4 years ago
- Z80 diassembler/assembler/emulator in golang☆12Oct 28, 2024Updated last year
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆11Jul 28, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- pure-python C types packer/unpacker☆19Mar 1, 2020Updated 6 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆20May 29, 2018Updated 8 years ago
- ☆15May 24, 2025Updated last year
- Mathematical Functions in Verilog☆99Mar 7, 2021Updated 5 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆114Apr 3, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An FPGA microcontroller that natively executes LISP☆94Jan 22, 2024Updated 2 years ago
- M-extension for RISC-V cores.☆32Nov 21, 2024Updated last year
- Stack CPU Work In Progress☆29Jul 16, 2026Updated 3 weeks ago
- ☆26Oct 8, 2019Updated 6 years ago
- A portable Forth compiler☆12Nov 24, 2024Updated last year
- MSX Documentation from various disk magazines like Sunrise Special, Future Disk etc☆11Feb 5, 2022Updated 4 years ago
- Minimal FPGA Processor Core for Stack-based CPU for CPLDs Using Bit-Serial Architecture☆18Sep 6, 2013Updated 12 years ago