A pipelined brainfuck softcore in Verilog
☆20Aug 5, 2014Updated 12 years ago
Alternatives and similar repositories for bfcpu2
Users that are interested in bfcpu2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- DirectDraw HAL implementation for VMDisp9x driver☆18May 9, 2026Updated 3 months ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- ☆18Aug 26, 2026Updated last week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Aug 4, 2026Updated 3 weeks ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 9 years ago
- APB Logic☆29Aug 6, 2026Updated 3 weeks ago
- MLFlow End to End Workshop at Chandigarh University☆11Feb 3, 2023Updated 3 years ago
- [WIP] ConfigX - Settings Management☆13Mar 6, 2024Updated 2 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Open Source Software development Kit for Graphics GPU for Xilinx Zu+ Platform.☆19Feb 28, 2025Updated last year
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 14 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- n-dimensional kdtree spatial indexing☆17Apr 7, 2022Updated 4 years ago
- Z80 diassembler/assembler/emulator in golang☆12Oct 28, 2024Updated last year
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆11Jul 28, 2019Updated 7 years ago
- ☆11Sep 15, 2015Updated 10 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- pure-python C types packer/unpacker☆19Mar 1, 2020Updated 6 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- Forth for the 8051☆33Dec 28, 2017Updated 8 years ago
- ☆15May 24, 2025Updated last year
- Mathematical Functions in Verilog☆99Mar 7, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆115Apr 3, 2020Updated 6 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- M-extension for RISC-V cores.☆33Nov 21, 2024Updated last year
- Stack CPU Work In Progress☆29Jul 16, 2026Updated last month
- A fast, deterministic, non-cryptographic hash for use in hash tables for Rust☆15Jan 12, 2021Updated 5 years ago